Connecting it all with metal
By now your placement has parked every standard cell in its slot and clock-tree synthesis has wired up the clock. But step back and look at the chip and you'll notice something unsettling: it's a city of buildings with no roads. Every cell has input and output pins sitting there, electrically isolated, waiting to be connected. The netlist says *"this NAND's output must reach those three flip-flop inputs"* — but nothing physically carries that signal yet. Routing is the step that lays down the metal that actually makes those connections.
Think of it as paving roads between addresses you've already assigned. The router's job is to draw a continuous strip of metal from every driver pin to every load pin it must feed, for every net in the design — and a modern chip has millions of nets. It can't just draw straight lines, because the wires would cross and short together. Instead it threads them through a stacked grid, the way a city packs traffic onto surface streets, overpasses, and tunnels so the cars never collide.
The metal stack (BEOL)
The transistors themselves live at the very bottom, etched into the silicon — that layer is the front end of line, or FEOL. Everything stacked *above* them is the wiring, and that's the back end of line, or BEOL: a sandwich of metal layers separated by insulator, connected vertically at chosen spots. This is your road network, and it is genuinely multi-level — think a dozen or more floors of highway stacked one above the next, each floor running its lanes in one direction so neighboring floors cross at right angles instead of fighting for the same lane.
Here's the part that matters most for a back-end engineer: the floors are not the same. The lowest metals (call them M1, M2) are thin and narrow — fine for short local hops between adjacent cells, but a lot of resistance per unit length, like a crowded one-lane alley. The upper metals are thick and wide — low resistance, built for long cross-chip journeys and for the power grid, like a six-lane freeway. So the router doesn't treat layers as interchangeable: short local nets stay down low, long timing-critical nets and power get promoted upstairs where the metal is fat and fast.
# Resistance of a wire segment (intuition, not a tool command) # R = rho * Length / (Width * Thickness) # Thinner + narrower lower layers -> small (W * Thickness) -> larger R. # Same length on a thick upper layer is far less resistive.
Global → detailed routing
You don't route a whole chip in one shot any more than a navigation app computes your trip lane-by-lane before you've even left the driveway. The router works in two passes, coarse then fine, and the difference between them is the whole mental model here.
Global routing plans at the level of regions. The chip is chopped into a coarse grid of tiles (often called *gcells*), and for each net the router decides roughly *which tiles it will pass through and which layers it will ride on* — without drawing a single exact wire yet. It's the highway-planning view: "this signal goes northeast across these neighborhoods, mostly on the upper floors." Crucially, global routing also tallies how many wires want to cross each tile boundary, so it can see trouble — too many cars aiming for the same on-ramp — before committing.
Detailed routing then does the real paving. It takes the global plan and lays down actual metal on the legal tracks — the pre-defined lanes on each layer — picking exact widths, exact positions, and exact via spots, snapping everything to the grid the foundry allows. This is where the wires become real geometry instead of intentions.
- Global routing: divide the chip into coarse tiles, assign each net a rough path and a layer budget, and estimate where wires will pile up.
- Track assignment: hand each net specific lanes on its chosen layers, spreading traffic so the detail step has room to work.
- Detailed routing: draw the exact metal segments and vias, snapped to legal tracks and grid positions.
- Search-and-repair: hunt down the remaining rule violations and rip-up-and-reroute the offending wires until the layout is clean.
Vias & layer changes
A signal can't reach its destination on one floor alone — sooner or later it has to change layers, the way a driver leaves the surface street to get onto the overpass. The metal layers are insulated from each other by design, so the only place a wire can hop between two adjacent floors is through a deliberate vertical connection punched in the insulator: a via. Vias are the on-ramps and off-ramps of the metal stack.
One via connects only two adjacent layers — M1 to M2, M2 to M3, and so on. To climb from a low layer all the way up to a thick upper layer, the router builds a via stack: a column of vias, one per floor, threaded straight up through the levels. That's how a signal coming off a cell pin down on M1 gets hoisted onto an M6 freeway and back down again to reach its load.
Congestion & DRC during routing
Some neighborhoods of the chip want far more wires running through them than there are lanes to carry them. That's congestion: demand for routing tracks exceeding the supply in a region. It usually traces back to choices made earlier — cells packed too tightly during placement, or a hot spot where many nets converge — which is why congestion is the back-end engineer's loudest signal that the floorplan or placement needs another look. When a region is over-congested, the detailed router simply can't fit all the wires legally, and you get either failures or ugly detours that lengthen wires and hurt timing.
And the router can't just cram metal wherever it fits — every wire it draws must obey the foundry's rules, the design rules, as it goes. Two wires on the same layer must stay at least a minimum distance apart or they'd short or be unmanufacturable; each wire has a minimum width; vias have their own enclosure and spacing rules. The router is essentially solving a giant packing puzzle where every piece must respect a rulebook written by the fab.
When the router does hit a violation it can't avoid in one pass, it falls back on rip-up and reroute: tear out the offending wires, then lay them down again along a different path that clears the conflict. Imagine repaving one stretch of road to relieve a jam, then checking whether you've accidentally created a new one two blocks over. It's iterative by nature, which is why routing a large block can run for hours.
Wires aren't free (RC)
Here's the idea that carries you straight into the next guide. Back in the front-end world, a wire was practically a free, instantaneous connection — a line on a schematic. Down here it is a physical strip of metal, and physical metal has two unavoidable properties: resistance (R), because the metal resists current, and capacitance (C), because the wire sits next to other conductors and stores charge between them like the plates of a tiny capacitor.
Together those give every wire a delay. The intuition is simple: a signal can't flip a wire's voltage instantly, because it must first push current *through* the resistance to charge up the capacitance — and the bigger that R times C product, the longer the wire takes to settle. A long net on a thin lower layer is the worst of both worlds: lots of resistance from the skinny metal, and lots of capacitance from the length. That's the deeper reason long nets get promoted to the thick upper layers — fatter metal cuts R and the delay drops.
# Why a wire now costs time (intuition, not a tool command) # wire delay grows with R * C # R larger on thin/narrow lower layers # C larger for long wires and tightly-packed neighbors # => long net on thin metal = slow. Same net on thick upper metal = faster.