Placing a Million Cells

From floorplan to a sea of cells

In the last guide you set up the floorplan — you fixed the chip's outline, parked the big blocks (memories, analog islands), and drew the rings and stripes of the power grid. Think of it as an empty open-plan office: the walls are up, the elevators and the power conduits are in, but not a single desk has been placed. Placement is the step that brings in the desks — and there are a *lot* of them.

Those desks are standard cells: the small, pre-designed logic bricks (an AND gate, a flip-flop, a buffer) that your synthesis tool emitted. Every cell is built to the same height so they snap into horizontal rows like books on a shelf, but they vary in width depending on how much logic they hold. A real block can hold hundreds of thousands to a few million of them. Placement decides the (x, y) home of every single one.

And placement does not happen in a vacuum — it has to leave room for the wires that come later in routing, dodge the blockages the floorplan reserved, and respect the rows the standard cells must align to. Get it wrong and the chip is unroutable or fails timing, no matter how clever the rest of the flow is. That is why placement sits early and matters enormously.

Global vs detailed placement

The tool does not drop a million cells into their final spots in one shot — that problem is far too big to solve exactly. Instead it works in two passes, coarse then fine, the way you might first decide *which room* each piece of furniture goes in before sliding each chair into place.

Global placement is the coarse pass. It treats cells almost like a fluid: it spreads them across the area to roughly balance density and pull connected cells together, optimizing a cost that blends total wire length and crowding. At this stage cells can sit *anywhere* — they may overlap, and they need not line up with the rows yet. The goal is a good overall arrangement, not a buildable one.

Detailed placement is the fine pass. It takes that rough cloud and nudges each cell into a real, legal home — snapped onto a row, aligned to the placement grid, no overlaps — while disturbing the global picture as little as possible. It does local clean-up: swapping neighbors, sliding cells along a row, filling gaps. Think of global placement as deciding the neighborhoods and detailed placement as parking each car neatly between the lines.

Density & congestion

Two words sound alike but mean very different things, and mixing them up is the classic beginner trap. Density (or utilization) is about *floor space* — how much of the available area is filled with cells. Congestion is about *wires* — how many connections want to thread through a region versus how many wire tracks actually fit there. You can have one without the other.

Utilization is the simple, honest number: the fraction of the placeable area that cells occupy.

utilization = (total cell area) / (placeable row area)

# e.g. 0.72  ->  72% full, ~28% left as breathing room
# typical placement target ~0.60-0.80 depending on the design

Utilization is just 'how full is the room.' Pack it too tight and there is no slack left for buffers, clock cells, and the wires routing must squeeze in later.

Here is the subtlety: a region can be only moderately full yet hopelessly congested, because a knot of heavily-connected cells landed there and far more wires want to cross that tile than there are metal tracks to carry them. It is the difference between a parking lot that is 70% full (fine) and a single exit where every car tries to leave at once (gridlock). Placement watches both, because routing later can only succeed if the wires physically fit.

Placement-driven timing

Up to now we have talked about space and wires. But placement is also timing-aware — arguably its most important job. Remember that a signal needs time to travel down a wire, and longer wires mean more delay. So the tool reads the timing constraints and tries to keep cells that sit on a tight path physically close together, shortening the wires between them.

The path that matters most is the critical path: the slowest route between two registers, the one with the least slack to spare. If placement lets a critical path's cells drift far apart, the wire delay alone can blow your timing budget — and no amount of later optimization fully recovers it. So the tool gives those cells a kind of magnetic attraction, pulling them tight while still respecting density and congestion.

This is the timing target the tool is placing against — a clock period it must fit every register-to-register path inside:

# Clock the design is placed to honor (vendor-neutral SDC)
create_clock -name CLK -period 1.25 [get_ports clk]   ;# 800 MHz

# A signal launched at one register must arrive at the next
# WITHIN one period (minus setup) — placement keeps the cells
# on each path close so wire delay does not eat that budget.

The clock period is the deadline. Placement shortens the wires on the tightest paths so the signal still makes it from one flip-flop to the next in time.

Legalization

After global and detailed placement, cells are *almost* where they belong — but a few may still overlap a sliver, sit a hair off the grid, or straddle a row boundary. Legalization is the tidy-up pass that makes the placement strictly *legal*: every cell snapped onto a row, aligned to the manufacturing grid, sitting flush against its neighbors with no overlap and no illegal gap.

Picture books shoved roughly onto a shelf, some tilted, some overhanging the edge. Legalization is the librarian who slides each one until it sits squarely on a shelf, spine aligned, none overlapping. Crucially, it tries to move each cell the *smallest* distance that fixes it — because every cell it shifts changes wire lengths and can perturb the timing the previous passes worked so hard to achieve.

Run global placement: spread cells to balance density and pull connected cells together, overlaps and off-grid positions allowed — this is the rough draft.
Run detailed placement: nudge cells onto rows and into a clean local arrangement, refining wire length and congestion without disturbing the global picture.
Legalize: snap every cell to a legal row-and-grid position with no overlaps, moving each the minimum distance so timing and congestion stay close to what the earlier passes found.
Re-check timing and congestion on the now-legal layout; if a region got worse, the tool can locally re-place and re-legalize before handing off to clock-tree synthesis and routing.

Reading a congestion map

Open a placement in the tool's GUI and ask for a congestion map, and you get a picture that looks exactly like a weather radar laid over the chip. The whole die is diced into a grid of small tiles, and each tile is tinted by how crowded its wiring is — specifically, by demand versus supply: how many wires want to cross that tile compared to how many metal tracks are available to carry them.

# Per-tile congestion (the number behind each color)
overflow = wires_demanded - tracks_available

#   overflow <= 0   ->  cool (blue/green): wires fit, healthy
#   overflow  > 0   ->  hot  (yellow/red): more wires than tracks -> trouble

Each colored tile is just demand minus supply. Cool means the wires fit; hot means too many wires want through too few tracks.

So you read it like heat: broad blue and green is calm, healthy, routable — the wires fit comfortably. Yellow is getting tight. Angry red and orange patches are hotspots where routing will likely fail because more wires want through than there are tracks to hold them. A good placement looks mostly cool and even; a sea of red, or a few fierce blotches, is a warning before you ever start routing.

What causes a red blob? Often a knot of densely-connected logic packed too tightly, a spot where many wires must funnel past a hard macro, or a corner the floorplan starved of routing space. The fixes echo earlier sections: let the tool spread the cells in that tile to lower local density, add or adjust placement blockages to steer cells away, or revisit the floorplan if a macro is choking a whole channel.