What "physical design" means
In the front-end track, synthesis handed you a netlist: a list of real gates plus the wires connecting their pins. It tells you *what* the chip is made of — this NAND drives that flip-flop — but it says nothing about *where* anything sits. A netlist is pure connectivity; it has no geometry at all. Picture a wiring diagram for a house that names every outlet and switch and which wire joins which, but never says which room anything is in. That is exactly the gap physical design exists to close.
Physical design (the *back end*, or place-and-route for short) is the craft of turning that flat, place-less netlist into a concrete arrangement on silicon: every standard cell gets an *(x, y)* coordinate, and every wire becomes an actual strip of metal running between pins. Where the front end asked "does the logic behave?", the back end asks the brutally physical question: "can all of this actually *fit*, connect, run fast enough, and survive being powered on?"
The flow you are starting has a fixed order, and each step depends on the one before it: floorplan → place → clock-tree synthesis → route → extract + timing signoff → physical verification (DRC/LVS) → power signoff → tapeout. This guide is the very first rung — the floorplan — because you cannot place a cell, route a wire, or check timing until you have decided the shape of the land they all live on.
Netlist → geometry
Let's make the "no geometry" idea concrete. A netlist instance looks like a part with named pins wired to nets — the same structural form you saw at the end of synthesis. Read the snippet below and notice what is *missing*: there is not a single coordinate, size, or layer anywhere. The tool knows these two cells are connected; it has no idea whether they end up touching or a millimeter apart.
// Netlist: connectivity only — NO location, NO size, NO layer NAND2_X1 u_g ( .A(a), .B(b), .Y(n1) ); // where is u_g? unknown DFF_X1 u_q ( .D(n1), .CLK(clk), .Q(q) ); // where is u_q? unknown // 'n1' says u_g.Y connects to u_q.D — but not how far the wire must travel
Physical design adds three things the netlist lacks. First, a place for every cell — an *(x, y)* on the silicon, snapped onto fixed rows like books onto shelves. Second, real wires — each net becomes physical metal on one or more routing layers, with actual length, width, and bends. Third, a sense of distance — once cells have positions, the tool finally knows a wire is 5 µm or 500 µm long, and *that length costs real time*, because a longer wire has more resistance and capacitance (RC) for the signal to charge.
Die, core & the floorplan
Before placing anything, you decide the *shape of the land*. The die is the whole rectangle of silicon you will cut from the wafer — the property line. Just inside it sits the core: the usable interior where your standard cells and rows live. The ring of space between core edge and die edge is where the I/O pads and seal ring go — think of it as the sidewalk and fence around a buildable lot. The core is almost always a clean rectangle, because standard cells live in straight, equal-height rows, and rows pack most efficiently into rectangular land.
Floorplanning is drawing this plan before a single cell is placed — and the city-planning analogy is exact. A planner doesn't drop houses at random and hope; they first lay out districts, set aside land for the big civic buildings, route the main roads, and run the water and power mains. Only *then* do individual houses fill in the blocks. Your floorplan does the same: fix the die and core size, reserve regions for the big blocks, plan the wide channels signals will travel through, and lay the power grid — all before the flood of tiny standard cells arrives.
Two numbers anchor the plan: the core area (how much buildable land you have) and the aspect ratio (its width-to-height shape). A near-square core keeps the longest possible wire short and balanced; a long thin core can starve a far corner of routing room. You are choosing the lot before you know exactly how the furniture will arrange — which is why floorplanning is equal parts arithmetic and judgment.
Placing macros & I/O
Not everything in your design is a tiny standard cell. Some pieces are macros — large, pre-built, fixed-shape blocks like SRAM memories, PLLs, or analog IP. If standard cells are houses, macros are the stadiums and shopping malls: they occupy big rectangular footprints, they have hard edges nothing else may overlap, and *you place them by hand, first.* Everything else flows around them, so getting them wrong poisons the whole plan.
Good macro placement follows a few stubborn rules of thumb. Push macros to the edges and corners of the core, like wardrobes against the walls, so the center stays open for the sea of standard cells. Orient each macro's pins to face inward, toward the logic that talks to it, so those connections stay short — a memory with its data pins facing a blank die edge wastes every wire that must crawl back around it. And leave a clear channel (a halo) of empty space around each macro so signals and power have room to route past, the way you leave aisles around furniture.
- Place the macros first, by hand: shove the big fixed blocks to edges and corners and orient their pins toward the logic that uses them, keeping a routing halo around each.
- Assign the I/O — decide where signals and power enter the die. Group related pins together and put each I/O near the on-chip logic it serves, so the wire from pad to logic stays short.
- Leave the core interior open. The wide rectangular space you protect in the middle is where the automatic placer will later pour in the thousands of standard cells.
- Sanity-check the channels: trace, in your head, the busiest connections and make sure there is open lane for them to travel — before any cell is placed.
Utilization: how full is too full?
Here is the question every floorplan has to answer: how tightly should you pack the cells into the core? Pack too loosely and you waste expensive silicon; pack too tightly and the wires have nowhere to run and the design becomes impossible to route. The single number that captures this is utilization — and intuitively it is just *how much of your buildable land is occupied by buildings.* A nearly empty lot is cheap to wire but wasteful; a lot crammed wall-to-wall leaves no room for the roads.
Concretely, utilization is the ratio of the area of all your cells to the area of the core they sit in:
utilization = total_cell_area / core_area # Example: 0.42 mm^2 of cells in a 0.60 mm^2 core utilization = 0.42 / 0.60 = 0.70 # 70% full # So: core_area = total_cell_area / target_utilization # 0.42 / 0.65 ~= 0.646 mm^2 of core to aim for ~65% full
Early in floorplanning you typically aim for roughly 60–70%. That deliberately-left gap is not waste — it is the breathing room the router needs for wires, plus space for the buffers and clock-tree cells that later steps will *add* to your design. If you pack to 90% on day one, you have quietly promised there is room for wires and future cells that simply isn't there, and you will pay for it as unroutable congestion downstream.
The power-grid skeleton
The last thing the floorplan lays down — and one of the first things to *exist physically* — is the power delivery network, the PDN. Every one of those thousands of cells needs a steady supply voltage and a ground return, and that power has to reach them through metal, not magic. So before the cells even arrive, you build a skeleton of power wiring: like running the water and electrical mains down every street *before* the houses are built, because you can't tear up a finished neighborhood to add a water main.
Picture it as a literal grid drawn in metal. Wide rings of metal circle the core carrying power and ground; from them, a regular lattice of straps runs across the chip — horizontal straps on one metal layer, vertical straps on another, stitched together at every crossing so current can flow around obstacles. Down at the bottom, thin rails run along every standard-cell row, tapping the straps above so each cell can sip power right where it sits. Rings feed straps; straps feed rails; rails feed cells — a hierarchy from wide highways down to neighborhood streets.
With the floorplan complete, the land is ready: die and core are sized, macros and I/O are anchored, utilization gives the placer room to work, and the power skeleton is laid. *Now* — and only now — the automatic placer can pour in the standard cells. That is exactly where the next guide picks up.