Two questions before tapeout
By now your block has been through a lot. You floorplanned it, placed the standard cells, built the clock tree, routed every net, extracted the parasitics, and closed timing. The layout *works* — in the model. But a working model is not a chip. Before you hand the design to the fab, you have to answer two blunt, separate questions, and both have to come back yes.
The first is: can the foundry physically build this? Your layout is millions of polygons on a few dozen metal and silicon layers. The fab makes them real with photolithography — printing each layer through a mask onto the wafer — and that process has hard physical limits. Wires can't be drawn thinner than light and chemistry can reliably reproduce; two shapes too close together will smear into each other. [[design-rule-check|Design Rule Check (DRC)]] answers this manufacturability question.
The second is: does this layout actually match the circuit I designed? Somewhere upstream you had a synthesized netlist — the official list of every transistor and every wire that should connect them. Place-and-route built a physical layout that is *supposed* to implement that netlist, but a swapped connection, a missing via, or a hand-edit can quietly break the match. [[layout-versus-schematic|Layout Versus Schematic (LVS)]] answers this correctness question. Together, DRC and LVS are the core of physical verification.
The foundry rule deck
Every fab and every process node ships a rule deck (often called the DRC runset or technology rules) — a long, precise document that says exactly what geometry the line can manufacture. Think of it as the building code for that process. A building code doesn't ask whether your house is beautiful or whether the rooms are in the right places; it says studs must be no more than 16 inches apart, a stairway must be at least this wide, a beam this thick. The foundry rule deck does the same for silicon, in nanometers.
The rules come in families. Width rules: a wire on this layer can't be narrower than X — go thinner and lithography won't print it cleanly. Spacing rules: two shapes on the same layer must stay at least Y apart, or they bridge into one. Enclosure rules: a via must be fully wrapped by the metal above and below by some margin, so a slight mask misalignment still lands on metal. Density rules: each layer must be neither too empty nor too full, because the chemical-mechanical polishing step planarizes better when copper is evenly spread. Hundreds to thousands of such rules, all numeric, all non-negotiable.
# Foundry rule deck — illustrative entries (units = nm) M1.W.1 : min_width(metal1) >= 32 # thinner won't print M1.S.1 : min_spacing(metal1) >= 32 # closer shapes bridge VIA1.EN.1: enclosure(metal1, via1) >= 5 # metal must wrap the via M1.DN.1 : 0.20 <= density(metal1) <= 0.80 # for uniform CMP polish
DRC: does it obey the rules?
DRC is the building inspector walking your finished layout with the code book in hand. It doesn't care what your chip *does*; it cares only whether every shape, on every layer, satisfies every rule in the deck. The tool sweeps the entire layout — billions of polygons — and flags each spot where a measurement falls short: this wire is 30 nm wide where the minimum is 32; these two pieces of metal are 28 nm apart where they must be 32; this via pokes past the metal that's supposed to enclose it.
Picture two parallel wires on the same layer drifting too close — a spacing violation. On the screen it's a hairline gap; on the wafer, photolithography would print them as one merged blob, shorting two nets that were never meant to touch. Or picture a wire that necks down to a sliver to squeeze past an obstacle — a width violation; the fab can't reliably reproduce something that thin, so it might print as a broken, open wire. DRC catches these *before* they become silicon, when fixing them is a routing tweak instead of a multi-million-dollar respin.
The output is a list of violations, each tied to a rule name and exact coordinates so you can jump straight to the offending geometry. Most are fixed by nudging or rerouting wires — often a small routing or ECO change. The loop is simple and unforgiving: run DRC, read the violations, fix them, run again. You repeat until the count reaches a single number.
# Run design-rule check against the foundry deck
drc -layout block.gds \
-ruleset foundryN_drc.rules \
-report block.drc.rpt
# Goal: this number is ZERO
Violations found: 0LVS: does it match the netlist?
DRC proves the layout is *buildable*. It says nothing about whether you built the right thing. That is LVS's job. The analogy is the as-built-versus-blueprint walkthrough: an inspector takes the architect's blueprint and the finished building and checks them device for device, wire for wire — is every room where the plan says, is every pipe connected to the right fixture? A house can be flawlessly constructed and still have the kitchen sink plumbed to the bathroom line. DRC would never notice; LVS exists to.
Mechanically, LVS does two things. First it extracts a netlist from the layout — it reads the polygons and works out, from the geometry alone, what transistors exist and what is wired to what. Then it compares that extracted netlist against the reference (schematic/synthesized) netlist the design was supposed to implement. It matches them up device by device and node by node. If they're identical in connectivity, LVS reports a clean match. If not, you get mismatches.
The classic failures read like a plumbing inspection gone wrong. A short: two nets that should be separate are connected in the layout — like two pipes accidentally joined. An open: a net that should be one piece is broken into two — a pipe that doesn't reach its fixture. A device mismatch: the layout has a transistor of the wrong size or count versus the schematic. Each is reported against the net or device name, so you can trace it back to the exact spot the layout diverged from intent.
Antenna & ERC
DRC and LVS have two close siblings that round out physical verification. The first is the antenna check. During manufacturing, the fab builds your chip one metal layer at a time, etching each with plasma. A long stretch of metal that's connected to a transistor gate but *not yet* connected to anything that can drain charge acts like a tiny antenna: it collects charge from the plasma, and that charge can build up enough to punch through and damage the thin gate oxide. The finished chip might be electrically perfect, yet the *process of building it* destroyed a transistor.
So the antenna check is really a DRC-style geometric rule about the manufacturing sequence: it limits how much exposed metal (the antenna 'ratio' of collecting area to gate area) can hang off a gate before that net reaches a safe path. The fixes are mechanical — add a small antenna diode to bleed the charge to ground, or 'jog' the wire up to a higher metal layer sooner so the dangerous antenna is broken into smaller pieces built at different times.
# Antenna rule (illustrative): exposed-metal area vs gate-oxide area antenna_ratio = metal_area_on_gate_net / gate_oxide_area # Violation when the accumulated ratio exceeds the foundry limit antenna_ratio <= ANT_MAX # else add an antenna diode, or jog to a higher layer
The second sibling is ERC — Electrical Rule Check. Where LVS asks 'do the connections match the netlist?', ERC asks 'are the connections *electrically sane*?' It hunts for things that are structurally legal but electrically wrong: a gate input left floating (connected to nothing, so its value is undefined), a power and ground net accidentally shorted, an output pin driven by two things at once. Think of it as the electrician's safety walkthrough after the plumber and the building inspector have signed off.
"Clean" — and why it's non-negotiable
In most engineering, 'good enough' is a sliding scale — 99% test coverage is great, a 0.1% performance miss is fine. Physical verification does not work that way. The only acceptable result for DRC, LVS, antenna, and ERC is clean: zero violations, zero mismatches, every check, across the entire chip. Not 'almost clean.' Not 'three known waivers we'll look at later' unless the foundry has formally signed each waiver. Clean.
The reason is brutal economics. Once you tape out — ship the final GDSII to the fab — a mask set for an advanced node costs millions of dollars and the wafers take weeks to months to come back. A single real DRC violation can mean a feature that won't print, killing the die. A single LVS short can mean the chip implements the wrong circuit — the silicon is functionally dead the moment it's powered on. Either way, the fix isn't a recompile; it's a respin: redraw, re-verify, re-mask, re-fabricate. Months and millions, gone.
- Run DRC against the foundry rule deck; fix every width, spacing, enclosure, and density violation until the count is zero.
- Run LVS: extract a netlist from the layout and compare it to the reference netlist; resolve every short, open, and device mismatch until it reports a clean match.
- Run the antenna check; add antenna diodes or jog wires to higher layers until every gate is within the foundry's antenna limit.
- Run ERC to catch floating nodes, power/ground shorts, and contention that LVS won't flag.
- Confirm all four are clean across the full chip — then, and only then, release the GDSII for tapeout.