The chip is mostly memory
Take the die photo of almost any modern phone or laptop processor and stare at it for a moment. You will see a few jagged, irregular patches — those are the CPU and GPU cores, the logic gates doing the actual computing. But surrounding and outweighing them are large, eerily smooth rectangles with a faint plaid texture, like graph paper seen from orbit. Those smooth blocks are memory. On a typical system-on-chip (SoC), on-chip memory — mostly cache — routinely occupies 40 to 60 percent of the silicon area, and sometimes more. The thing we call a 'processor' is, by area, mostly a place to keep numbers.
Why does memory deserve its own discipline, its own track, separate from the rest of digital design? Because that smooth plaid texture is the whole story. Logic is irregular: every gate connects to different neighbours, every block has a custom shape. Memory is regular: one tiny cell, copied across thousands of rows and thousands of columns, identical down to the last atom. That single difference — irregular versus regular — cascades into a completely different way of thinking about layout, electrical margin, manufacturing yield, and speed. By the end of this track you'll understand each memory type in detail; this rung hands you the map.
The memory hierarchy: fast and tiny, slow and vast
No single kind of memory is good at everything. A memory that is blazingly fast is also expensive and physically large per bit; a memory that holds a terabyte in your pocket is comparatively slow. So engineers don't pick one — they stack several, fast-and-small nearest the processor, slow-and-huge furthest away. This staircase is the memory hierarchy, and almost every performance story in computing is really a story about moving data up and down it.
CLOSER / FASTER / SMALLER / COSTLIER per bit
┌──────────────────────────────────────────────────────┐
│ Registers ~1 KB ~1 cycle in the core │
│ SRAM L1 cache ~32-64 KB ~4 cycles on-die │
│ SRAM L2 cache ~256KB-1MB ~12 cycles on-die │
│ SRAM L3 cache ~8-64 MB ~40 cycles on-die │
│ DRAM main mem ~8-64 GB ~200 cycles off-chip │
│ Flash / SSD ~0.5-4 TB ~50,000 cyc off-chip │
└──────────────────────────────────────────────────────┘
FARTHER / SLOWER / BIGGER / CHEAPER per bit
Cycle counts are rough, for a ~3 GHz core. One DRAM access
(~200 cycles) is ~200 wasted instruction slots if you wait.Read that table again and notice the cliff. Stepping from L3 SRAM to off-chip DRAM doesn't make things a little slower — it makes them roughly five times slower, and the next step to flash is hundreds of times slower again. Each technology earns its rung by being radically better at one thing: registers and SRAM are built from ordinary transistors right beside the logic, so they're instant but bulky; DRAM uses a clever one-transistor-one-capacitor trick to pack far more bits per square millimetre, at the cost of speed and a constant need to be refreshed; flash stores charge on a trapped 'floating gate' that survives power-off entirely, so it's permanent but slow to write. Later rungs dissect each of these.
The memory wall: why the cliff matters
Here is the uncomfortable truth that gives this whole track its urgency. For decades, processor speed grew far faster than memory speed. Logic followed Moore's Law and got dramatically quicker every couple of years; main-memory latency improved at a crawl. The gap between them widened until it became the dominant bottleneck — a phenomenon engineers named the memory wall. A modern core can execute several instructions per nanosecond, but a single trip to DRAM costs perhaps 60–100 nanoseconds. Do the arithmetic: the processor can sit idle for hundreds of instruction slots, drumming its fingers, waiting for one number to arrive.
This is why AI accelerators and GPUs increasingly live or die not on how many multiplications they can do, but on how fast they can be fed. Stacks of high-bandwidth memory sitting beside a giant GPU die are now among the most valuable rectangles in the entire electronics industry. Memory stopped being a passive afterthought and became the headline.
The universal array: rows, columns, wordlines, bitlines
Now the central idea that makes everything else click. Almost every memory ever built — SRAM, DRAM, flash, even ROM — is organized as a 2-D grid of cells, like seats in a vast theatre. To find one bit you need its row and its column, exactly like 'Row M, Seat 14'. The horizontal wire that selects a whole row is the wordline; raising it is like the usher announcing 'everyone in Row M, stand up'. The vertical wires that then carry the data of the selected cells in and out are the bitlines, one per column.
bitline0 bitline1 bitline2 bitline3
│ │ │ │
wordline0 ────────●─────────●─────────●─────────●────
[cell] [cell] [cell] [cell]
│ │ │ │
wordline1 ────────●─────────●─────────●─────────●────
[cell] [cell] [cell] [cell]
│ │ │ │
wordline2 ────────●─────────●─────────●─────────●────
[cell] [cell] [cell] [cell]
│ │ │ │
▼ ▼ ▼ ▼
┌───────────────────────────────────────┐
│ sense amplifiers + column mux (read) │ <- periphery
└───────────────────────────────────────┘
Raise ONE wordline -> that whole row drives its bitlines.
Sense amps at the bottom recover the tiny signals as 1s/0s.Notice the split that defines the whole craft: array + periphery. The array is the boring, beautiful, endlessly repeated grid of cells. The periphery is the ring of cleverness around it — the row decoder that turns an address into 'raise wordline 1,048,575', the sense amplifiers that detect the faint voltage a cell leaves on a bitline (often just a few tens of millivolts), the column multiplexers, the write drivers. The array gives you density; the periphery makes it usable. Hold this two-part picture in your head and every later rung — SRAM read margins, DRAM refresh, flash programming, sense-amp design — is just a closer look at one part of it.
Why a 6-transistor cell needs different rules than a logic gate
Here is the worked intuition that justifies treating memory as its own discipline. Consider the workhorse SRAM cell, the 6T bitcell: six transistors that hold a single bit. In a logic block, a designer might place a few hundred thousand custom standard cells. In a 32-megabyte cache, that same 6T cell is stamped out over 1.5 billion times, every copy identical, packed as tightly as the manufacturing process physically permits. That sheer multiplicity flips the economics of design on its head.
- Hand-optimised, not auto-placed. A logic standard cell is drawn once by the foundry and reused. An SRAM bitcell is drawn once too — but because it repeats a billion times, engineers agonize over every nanometre, using special relaxed 'memory design rules' the foundry grants only inside arrays. A 1% area saving on the cell is a 1% saving on a third of the chip.
- Statistics, not worst case. With a billion identical cells, the laws of large numbers bite. If even one cell in a million fails, your cache has a thousand dead bits. So memory designers reason in standard deviations — they need every cell to work out to 5 or 6 sigma, a margin a logic designer would find absurd, because they're betting against a billion dice rolls, not a thousand.
- Margin, not just function. A logic gate either computes the right answer or it doesn't. A bitcell can compute the right answer and still be a bad design — because reading it might disturb the very bit it's storing. Memory introduces a whole new axis, read/write margin (static noise margin), that has no real equivalent in logic. Keeping a cell both readable and writable is a tug-of-war we'll spend a full rung on later.
- Repair built in. No billion-cell array comes off the line perfect. So memory ships with spare rows and columns and a tiny controller that swaps a defective row for a spare — redundancy and repair. Logic has no such routine luxury; memory cannot live without it.
The map for this track
You now hold the two ideas every later rung leans on. First, the hierarchy: a staircase of memories trading speed for size, with the memory wall making that trade the central drama of computing. Second, the array + periphery model: a regular grid of cells addressed by wordlines and bitlines, wrapped in clever decoders and sense amplifiers. With this vocabulary, the rest of the track can zoom in: how the 6T SRAM cell really works, why DRAM must refresh, how flash traps charge for years, and how sense amplifiers tease a clean bit out of millivolts of signal.