The SRAM 6T Bitcell: Two Inverters That Remember

Two inverters in a staring contest

Imagine two people facing each other, each whispering to the other, "Whatever you just said, I'll say the opposite." If the first says "high," the second answers "low," which loops back and confirms "high" again. The conversation is self-consistent and never ends. That endless, self-reinforcing loop is exactly what a cross-coupled inverter pair does — and it is the heart of every SRAM bitcell.

An inverter in CMOS is just two MOSFETs: a PMOS pull-up that connects the output to VDD when the input is low, and an NMOS pull-down that connects the output to ground when the input is high. Wire the output of inverter A to the input of inverter B, and B's output back to A's input, and you have a latch with two stable states. Either A's output is high and B's is low, or the reverse. There is no third option, and — crucially — nothing in between is stable.

          VDD                 VDD
           |                   |
         [ PL ]              [ PR ]      <- PMOS pull-ups
           |                   |
    Q ----+----.         .----+---- QB
          |     \       /     |
          |      `-----'      |        <- cross-coupling wires
          |     .'     `.     |
         [ NL ]            [ NR ]      <- NMOS pull-downs
           |                   |
          GND                 GND

   Q  holds the bit (say '1' = high)
   QB holds its complement ('0' = low)

Adding the two doors: access transistors and the wordline

A latch that no one can talk to is useless. To read or write the cell, we add two more NMOS transistors — the access transistors — one on each storage node. Their gates are tied together to the wordline (WL). Their other terminals connect to a pair of vertical wires, the bitlines BL and BLB. Two inverters (four transistors) plus two access transistors makes six — hence 6T.

                 WL (wordline)
   ________________|________________
   |                                |
  [AL]  access                   [AR]  access
   |     transistor                |    transistor
   |                                |
   Q  o----[ inverter pair ]----o  QB
   |                                |
   |                                |
  BL                              BLB
 (bitline)                      (bitline-bar)

  WL = 0  -> AL, AR OFF -> cell isolated, holds its bit (HOLD)
  WL = 1  -> AL, AR ON  -> Q/QB connected to BL/BLB (ACCESS)

Here is the elegant division of labour. When the wordline is low, the access transistors are off, the cell is sealed off from the world, and the inverter loop quietly holds its bit. This is the *hold* state — and it's where the cell spends 99.99% of its life. When the wordline goes high, both doors swing open and the storage nodes are exposed to the bitlines. Now — and only now — can the outside world read what's inside or force a new value in.

Reading without breaking it

Reading an SRAM cell is a delicate operation, because the act of looking can change what you're looking at. Here's the sequence. First, both bitlines are precharged to VDD and left floating — think of them as two buckets filled to the brim. Then the wordline rises, opening the access transistors. The bitline on the side where the cell holds a 0 now has a discharge path to ground through the access transistor and the pull-down NMOS. That bitline slowly droops; its partner stays high. A sense amplifier (rung 5's topic) detects the tiny voltage difference — often just 50–100 mV — and amplifies it into a clean logic level.

But here's the danger. The bitline holding the 0-side was just precharged to VDD. When the wordline opens, that high bitline tries to *pull the internal 0-node upward* through the access transistor. If the internal node rises too far — past the switching threshold of the opposite inverter — the cell flips, and you've just destroyed the very bit you were trying to read. This is a read disturb, and avoiding it is the cell's central balancing act.

The defence is sizing. We make the pull-down NMOS *stronger* than the access transistor, so during a read it wins the tug-of-war and keeps the internal 0-node firmly near ground. The ratio of pull-down strength to access strength is called the cell ratio (or β ratio). A typical value is around 1.5–2.5. Bigger cell ratio means a safer read — but also a bigger, slower cell.

READ of a cell holding Q=1, QB=0

  Step 0  Precharge:  BL = VDD,  BLB = VDD   (both high)
  Step 1  WL -> 1:    access transistors ON

          BL  side (Q=1):  no discharge path -> BL stays ~VDD
          BLB side (QB=0): path to GND -> BLB droops

  Step 2  Sense:  V(BL) - V(BLB)  ~  +60 mV   -> read '1'

  DANGER on the QB side:
          BLB(=VDD) pushes charge onto QB(=0) node
          If QB climbs past V_trip of the left inverter -> FLIP!

  Guard:  make pull-down NMOS stronger than access NMOS
          cell ratio  CR = (W/L)_pulldown / (W/L)_access  >= ~1.5

Writing: forcing a flip on purpose

Writing is the mirror image of reading, and it exposes a beautiful tension. During a read we *fought* to keep the cell from flipping. During a write we *want* it to flip — but only the cell we've selected, and reliably every time. How do we overpower a latch that is actively holding its value? Brute force, applied cleverly.

To write a 0 into a cell currently holding a 1 (Q=1, QB=0), the write driver yanks the BL bitline hard down to ground while holding BLB high. The wordline opens, and now BL fights to pull the internal Q-node (sitting at VDD) down. The access transistor passes a strong 0, so it can drag Q down — *if* the access transistor is stronger than the PMOS pull-up that's trying to hold Q high. Once Q falls below the trip point of the right inverter, the regenerative loop takes over and slams the cell into its new state, completing the flip on its own.

This gives us the second sizing rule. For writes to succeed, the access transistor must be able to overpower the PMOS pull-up. So we make the pull-up *weak*. The ratio of pull-up strength to access strength is the pull-up ratio (PR), and we want it *small* — typically 0.5 or less. A weak pull-up is also why those access transistors don't need to be huge: they only have to beat a deliberately feeble PMOS.

A worked example: read vs. write on the same cell

Let's make the truce concrete with one cell and two operations back to back. Suppose the cell holds Q=1, QB=0. We'll first read it, then write a 0 into it, and watch how the *same* access transistor must behave differently — losing one tug-of-war and winning another.

1. Read. Precharge BL=BLB=VDD, raise WL. On the QB=0 side, the access transistor and pull-down NMOS form a divider between the high bitline and ground. The pull-down (cell ratio ~2) is the stronger device, so the QB node only nudges up a little — well below the trip point. The cell survives; BLB droops and the sense amp reads '1'.
2. Why it didn't flip. With cell ratio CR ≈ 2, the divider holds the internal 0-node at roughly VDD/(1+CR) ≈ 0.33·VDD. For a 1.0 V supply that's ~0.33 V, safely under the ~0.5 V inverter trip point. Margin to spare.
3. Write 0. Now the write driver pulls BL all the way to 0 V (BLB stays high). Raise WL. This time the access transistor on the Q side connects the internal Q-node (at VDD) to a grounded bitline.
4. The flip. Q is now pulled down through the access NMOS against the PMOS pull-up. Because the pull-up ratio PR ≈ 0.5, the access transistor wins: Q falls past the trip point, the left inverter starts driving QB high, QB feeds back and shuts off the PMOS holding Q — the loop regenerates and the cell settles into Q=0, QB=1.
5. Same transistor, two roles. In the read it *lost* (kept weaker than the pull-down → cell ratio). In the write it *won* (kept stronger than the pull-up → pull-up ratio). Both are true at once only because the pull-down is strong AND the pull-up is weak.

Numbers for a ~1.0 V cell (illustrative)

  Devices (W/L, relative strength):
    pull-down NMOS   strong   (ratio 2)
    access  NMOS     medium   (ratio 1)   <- pivot device
    pull-up  PMOS    weak     (ratio 0.5)

  Cell ratio   CR = pulldown/access = 2.0   -> read-safe
  Pull-up ratio PR = pullup/access  = 0.5   -> write-able

  READ  : internal 0-node rises to ~VDD/(1+CR) = 0.33 V  < V_trip (~0.5 V)  OK, no flip
  WRITE0: access (str 1) vs pull-up (str 0.5) -> access wins -> Q dragged to 0  FLIP

  Squeeze:  CR large (read) AND PR small (write)
            => pull-down >> access >> pull-up

Why six? The economics of the smallest decision

You might wonder why we don't just use one transistor per bit, like DRAM does. The answer is a trade between speed, simplicity, and silicon area. DRAM stores a bit as charge on a tiny capacitor — one transistor, one capacitor — so it's far denser. But that charge leaks, so DRAM must be refreshed thousands of times a second, and it's slower. SRAM's six transistors cost area, but buy you something precious: a bit that holds itself with no refresh, that can be read and written in a fraction of a nanosecond, and that's built from the very same CMOS logic as the processor around it — so it lives happily *on* the chip.

That's why SRAM is the on-chip workhorse: it forms the caches that sit nanometres from your CPU's execution units, the register files, the lookup tables inside routers. A modern processor can spend half its die area on SRAM. Each cell is laid out in a hyper-optimized, rule-bending shape (the 'thin cell') that foundries refine node after node — because shaving a few percent off a structure you replicate a billion times is worth enormous engineering effort.