Power Domains: Gating, Islands, and the Plumbing Between Them

One chip, many cities: the power domain

In rung 4 you learned a hard truth: even a transistor that is switched fully off still bleeds current. Leakage never sleeps. You fought it with transistors of different threshold voltages — slow-but-tight high-Vt cells off the critical path, fast-but-leaky low-Vt cells on it. That helps, but it has a ceiling. A high-Vt transistor leaks *less*; it does not leak *nothing*. Multiply a small leak by a few billion transistors and a chip that is doing absolutely nothing can still drain a battery overnight. To get leakage to truly zero in a block, you have only one option: take its electricity away entirely.

That single idea forces a change in how we think about a chip. Up to now you have probably pictured a chip as one circuit on one supply voltage — call it VDD — everywhere. But a modern system-on-chip is more like a country than a city: it is divided into regions, each with its own power policy. A [[ic-power-domain|power domain]] is a region of the chip whose supply and power state are controlled together as a unit — same voltage, same on/off control, same low-power intent. The CPU might be one domain, the GPU another, the always-on real-time clock a third. When the GPU is idle, its domain can be switched off completely while the CPU's stays alive, exactly the way you turn off the lights in rooms nobody is using without cutting power to the whole house.

Power gating: the master switch on the wall

So how do you actually take electricity away from a region? You put a switch in its supply line. This is [[power-gating|power gating]], and the cell that does it is a [[ic-power-switch-cell|power switch cell]] — physically just a big, wide transistor inserted between the always-on supply rail and the block's local rail. Turn that transistor on and the block sees full VDD; turn it off and the block is cut loose, floating, drawing essentially no leakage. Think of it as the master breaker on the wall feeding one room: flip it and that entire room is dead, no matter how many lamps are plugged in.

There are two flavours, named for which rail they sit on. A header switch is a PMOS transistor between the global VDD and the block's virtual VDD; switch it off and the top of the block is starved. A footer switch is an NMOS transistor between the block's virtual ground and the real ground; switch it off and the bottom is cut. Footers (NMOS) are smaller and conduct better per unit area, so they are common; but headers gate the supply itself, which can simplify some I/O cases. Either way the switch transistor is itself made of high-Vt silicon — it spends most of its life *off*, holding back the leakage of everything behind it, so the one transistor you leave in the path must leak as little as possible.

        global VDD  (always-on rail)
            |
          --+--   <- HEADER switch (PMOS, high-Vt)
           /        gated by SLEEP
            |
        virtual VDD  o-------------------+
            |                            |
        [  gated logic block:  ]   <- this whole domain
        [  the CPU, GPU, etc.  ]      goes to ~0 leakage
            |                            |
        virtual GND  o-------------------+
            |
          --+--   <- FOOTER switch (NMOS, high-Vt)
           /        gated by SLEEP
            |
        global GND  (always-on rail)

SLEEP = 0 -> switches ON  -> block powered, virtual rails = real rails
SLEEP = 1 -> switches OFF -> block cut off, leakage collapses to ~0

Isolation cells: don't let a corpse vote

Here is the first thing that goes horribly wrong the moment you turn a block off. The GPU domain is dark — but its output wires still run physically into the always-on CPU domain next door, which is wide awake and reading them. When a powered-down block's output is left floating, its voltage drifts to some indeterminate value, neither a clean 1 nor a clean 0. Feed that floating signal into a live gate and two bad things happen: the live gate may interpret it as a random value (corrupting the awake logic), and worse, an input stuck around mid-rail turns a CMOS gate's two transistors *both partly on*, opening a direct path from VDD to ground — crowbar current. You shut a block off to save power and instead set its neighbour on fire.

The fix is an [[ic-isolation-cell|isolation cell]]: a small gate placed on every signal crossing *out* of a switchable domain into an always-on one. While the domain is powered, the isolation cell is transparent — the real signal passes through. The instant before the domain shuts down, an isolation enable signal fires and the cell *clamps* its output to a known, safe constant — usually a hard 0 (an AND/NOR-style clamp) or a hard 1 (an OR-style clamp), whichever keeps the downstream logic happy. The receiving domain now sees a clean, stable value no matter how badly the dead domain's outputs drift. The corpse is no longer allowed to vote.

Level shifters and retention: bridging volts and remembering state

Isolation handles the *off* problem. Now meet the *different-voltage* problem. Recall the voltage island: a CPU at 0.9 V talking to a sensor block at 0.6 V. A logic '1' from the 0.9 V block is a 0.9 V signal — but to the 0.6 V block, 0.9 V on an input can over-drive its thin-oxide transistors, or simply confuse the level it expects. Going the other way is worse: a 0.6 V '1' arriving at a 0.9 V gate may sit below that gate's switching threshold, so it can't fully turn the gate's transistor off — the gate sits half-on, leaking crowbar current and reading the input wrong. Two regions at different voltages cannot just be wired together.

The bridge is a [[ic-level-shifter|level shifter]]: a cell on every signal crossing a voltage boundary, that translates a logic value from the source voltage to a clean version at the destination voltage. A *down* shifter (0.9 V → 0.6 V) is mostly a buffer with the right supply. An *up* shifter (0.6 V → 0.9 V) is cleverer — it usually needs *both* supplies and a small cross-coupled pair that snaps a weak low input up to a full high output. In a power-gated design you'll often find a combined enable level shifter that does isolation and level shifting in one cell, because the boundaries frequently coincide.

One problem remains, and it's the cruellest. When you cut a domain's power, every flip-flop inside it forgets. The CPU was in the middle of a calculation; now its registers are garbage. Booting from scratch every wake-up would be slow and burn its own energy. The answer is the [[ic-retention-register|retention register]]: a special flip-flop with a tiny secondary latch — a "balloon" or shadow cell — powered by the always-on supply through a thin, ultra-low-leakage path. Just before shutdown a save signal copies the register's value into the balloon; the main flip-flop then loses power and leaks nothing; on wake, a restore signal copies the value back. The domain wakes up exactly where it left off, as if it had only blinked.

The choreography: a wake/sleep sequence

Now watch all four cell types dance together, because order is everything. If you power a block down before isolating it, its outputs float through the always-on logic and you get the crowbar fire from earlier. If you restore retention before the rails are stable, you copy garbage back in. The save, isolate, gate, restore steps must fire in a strict sequence, usually driven by a small always-on power management unit (PMU). Here is the canonical going-to-sleep then waking-up cycle for one switchable domain.

1. Stop the clock. Quiesce the domain — finish or halt outstanding work and gate its clock so nothing is mid-transition. A block must be logically idle before you yank its power.
2. Save state (assert save). The retention registers copy their live values into their always-on shadow latches. State is now safely parked outside the about-to-die logic.
3. Assert isolation. Every output crossing into an always-on domain is clamped to its safe constant by its isolation cell. The boundary is now sealed.
4. Switch off power (assert sleep). The power switch cells open, collapsing the virtual rails. Now — and only now — is the domain's leakage driven to essentially zero.
5. …sleep… The domain sits dark, drawing nothing. The always-on logic carries on, seeing only clean clamped values where the dead domain used to talk.
6. Switch power back on (release sleep), then wait. The power switches re-engage — ramped gradually to avoid [rush current](#) inrush — and you wait for the virtual rails to climb back to a stable VDD before trusting anything inside.
7. Restore state (assert restore). With rails stable, the retention registers copy their saved values back from the shadow latches. The domain now holds exactly the state it had before sleeping.
8. Release isolation, then start the clock. Drop the isolation clamps so real signals flow across the boundary again, finally ungate the clock, and the domain resumes as if nothing happened.

signal        going to SLEEP            staying asleep    WAKING UP
            ------------------------|                |----------------------
clock     ___|‾stop‾|________________________________________|‾run‾|_______
save      ________|‾|___________________________________________________   (pulse)
isolation _________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|________
sleep     ____________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________________
restore   ___________________________________________________|‾|________   (pulse)
rails     ‾‾‾‾‾‾‾‾‾‾‾‾\__________ 0 V (no leakage) ________/‾‾‾‾‾‾‾‾‾‾‾‾‾

KEY ORDERING RULES:
  isolate  BEFORE  sleep        (seal outputs before they float)
  sleep    AFTER   save         (don't kill power before state is parked)
  restore  AFTER   rails stable  (don't reload state into a half-dead rail)
  isolation released LAST        (only un-clamp once the domain is fully alive)

Where this is heading: making it dynamic and formal

Step back and look at what you've built: a chip carved into power domains and voltage islands, with switches to kill leakage, isolation to seal off the dead, level shifters to bridge voltages, and retention to remember. This is real, profound power saving — the reason your phone lasts a day instead of an hour. But notice two things are still missing, and they're exactly the next two rungs.

First, so far a domain is either fully on or fully off, and an island is fixed at one voltage. But a CPU doesn't need full speed to read email. What if you could *slow the clock and drop the voltage* when the workload is light, and crank both back up only when needed? Because dynamic power scales with frequency and with voltage *squared*, even a modest voltage drop saves enormous energy. That continuous, on-the-fly tuning is Dynamic Voltage and Frequency Scaling (DVFS) — turning the static islands of this rung into a dial you can spin in real time.