Why planar ran out
Start with the one part a transistor cannot do without: control. A MOSFET is a switch, and the gate is the hand on the switch. When you put voltage on the gate, it should reach down into the silicon channel and either invite current through (on) or pinch it off completely (off). For decades, the recipe for a *better* switch was simply *smaller*: every shrink made the device faster, cheaper per transistor, and — under Dennard scaling — lower-power all at once. That happy bundle is what people really mean when they invoke Moore's Law.
The trouble is geometry. In a classic planar transistor the channel is a flat strip lying on the surface, and the gate is a flat plate sitting on *top* of it — touching the channel on one side only. That was fine while the channel was long. But as each new node made the channel shorter, the source and drain at its two ends crept close enough to start tugging on the channel themselves, competing with the gate. The single-sided gate could no longer fully shut the current off. The switch began to leak in the off state — current trickling through a transistor that is supposed to be closed.
Leakage is not a tidy rounding error. Multiply a tiny off-state trickle by billions of transistors and you get a chip that burns power doing nothing — the same power wall that ended Dennard scaling around 2005–2006 and forced the industry into multi-core. By roughly the 22nm era, the flat transistor had simply run out of road. To keep shrinking, the channel had to leave the plane.
The FinFET: standing the channel up
The fix is almost embarrassingly physical: if the gate can only touch the channel from above, then *give it more channel to touch.* Take the flat strip of silicon and stand it up on its edge into a thin vertical wall — a fin — then drape the gate down over it. Now the gate hugs the fin on three sides: left face, top, right face. Three hands on the switch instead of one. That is the FinFET, and it carried the industry from about 22nm down through the single-digit nodes.
Why three sides help is the whole point. The more of the channel's surface the gate surrounds, the more completely it owns the voltage inside — and the less room the source and drain have to sneak in and prop the current open. Wrapping the channel restores the off-state the planar device had lost, so the channel can be short again without leaking. A side bonus: you can make a fin *taller* to get more current-carrying width without using more floor area, or stand several fins side by side for a stronger transistor.
PLANAR FinFET (gate on 3 sides)
------ ------------------------
gate [ gate ]
======== ===|######|===
-------- |######| <- gate wraps
channel |######| L / top / R
============ ----|fin |----
substrate channel (stood up)
============
1 side touched substrate
-> short = leaky 3 sides touched -> better gripGate-all-around / nanosheet
Three sides beats one, so the obvious question is: why stop at three? Push the nodes far enough and even a FinFET's open bottom edge starts to leak — the gate still has a blind spot. The answer is to close it: gate-all-around (GAA), the structure entering production at the 3nm-class node and below (Samsung's 3nm GAA, TSMC's N2, Intel's RibbonFET-class device). Instead of a tall fin, the channel becomes a short stack of horizontal silicon nanosheets (sometimes thin wires), and the gate material is grown *completely around* each sheet — all four sides. The gate now fully encircles the channel. There is no blind edge left for the source and drain to exploit.
GAA also gives designers a knob FinFETs never had. A fin's drive strength comes in whole-fin steps — one fin, two fins, three — a coarse staircase. A nanosheet's width can instead be tuned continuously: wide sheets for transistors that must drive hard, narrow sheets where power matters more. For the standard cells that place-and-route tools stamp down by the million, that finer control is a real lever on power and area.
FinFET GAA / NANOSHEET ------ --------------- [ gate ] ___gate wraps ALL 4 sides___ =|####|= ( ====sheet==== ) <- gate |####| gate on ( ====sheet==== ) all |####| 3 sides ( ====sheet==== ) around -|####|- "-------------" each sheet ====== ============ substrate substrate bottom edge open no blind edge: fullest grip
CFET: stacking n over p
GAA wraps the channel as tightly as a single device can. So the frontier moves to a *different* axis. Every logic gate in CMOS needs two flavours of transistor — an n-type and a p-type — sitting side by side, and that side-by-side pair eats real floor area. The next idea refuses to lay them next to each other at all: complementary FET (CFET) stacks one transistor directly *on top of* the other, n over p, in the vertical direction. Two devices now occupy roughly the footprint of one.
That is a big deal because the easy area wins are gone — you cannot keep halving feature sizes forever, and the wires between transistors (interconnect) are now as much a bottleneck as the transistors themselves. Stacking devices vertically buys density along an axis that *isn't* yet crowded. CFET is genuinely future / research-stage, not in volume production — it is hard to build (you must fabricate good transistors stacked on top of already-built ones) — but it is the leading candidate for where the single device goes after GAA, and a clear signal of the theme of this whole rung: when you run out of room sideways, build upward.
A peek at backside power
Even a perfect transistor is useless if you cannot feed it cleanly. Traditionally *everything* reaches the device from above: the signal wires that carry logic *and* the fat power rails that deliver current all share the same crowded stack of metal layers on the front. They fight for room, and the thin power wires drop voltage on the way down — the IR-drop problem from the physical-design rung.
[[backside-power-delivery|Backside power delivery]] (Intel's PowerVia, and the TSMC/imec versions arriving around the 2nm generation) does something almost obvious in hindsight: flip the wafer over and route the power network on the *back* of the silicon, leaving the front entirely for signal wires. Power comes up from below; signals stay on top; the two stop competing. Power gets to the transistors with less loss, and the freed-up front-side metal makes routing easier. We cover the wiring side of this in the interconnect guide — here just hold the picture: once the device went 3D, even its power supply moved to a new dimension.
Where the roadmap goes
Step back and the arc is one straight line — *the gate keeps gaining ground on the channel, and the device keeps gaining dimensions.* Each rung answered the failure of the rung below it:
- Planar — gate on one side; ran out of control as channels shrank, and leaked.
- FinFET (~22nm onward) — stand the channel up; gate on three sides wins back control.
- Gate-all-around / nanosheet (~3nm and below) — wrap the gate fully around stacked sheets; all four sides, plus tunable sheet width.
- CFET (future) — stop spreading sideways; stack n over p vertically to reclaim area along a fresh axis.
- Backside power (≈2nm era) — move the power network to the back so it stops fighting the signal wires.
Where next? The pure-shrink era is over, so the frontier splits. One branch keeps stacking and integrating — eventually using chiplets and advanced packaging to build a 'system' from many small dies instead of one heroic monolith (the next guides in this track). Another branch asks whether silicon CMOS is even the endpoint, exploring beyond-CMOS devices that switch on different physics entirely. The shared lesson of this guide is the one that carries through the rest of the rung: when a flat, two-dimensional way of building hits a wall, the answer is almost always another dimension — taller fins, wrapped sheets, stacked transistors, backside power, stacked dies.