The promise of Moore's law
In 1965 Gordon Moore noticed something almost too good to be true. The number of transistors you could pack onto a chip was doubling at a steady, almost clockwork pace — and he bet it would keep going. He was right for half a century. That bet is [[moores-law|Moore's law]], and it is the reason the supercomputer of 1975 now sits in your pocket and costs less than dinner.
Read the law carefully, though, because almost everyone misremembers it. Moore's law is a statement about count — how many transistors fit in a given area, doubling roughly every two years. It says *nothing* about how fast those transistors switch, how much power they burn, or how cheap each one is. People felt all three of those things improve at once for decades and quietly folded them into 'Moore's law' in their heads. They were actually riding a *second*, separate gift — and that one had a shorter lease.
Dennard scaling: the free lunch
Here is the gift people forget to name. In 1974 Robert Dennard worked out the bookkeeping of shrinking a transistor: if you scale every dimension down by the same factor *and* drop the supply voltage by that same factor, then the power packed into each square millimetre stays constant. Smaller transistors, lower voltage, same heat per area. This is [[dennard-scaling|Dennard scaling]], and it is the real engine behind 'computers just keep getting better.'
Sit with how generous that is. Each new generation gave you transistors that were smaller (thank you, Moore), *and* faster (shorter distances, snappier switching), *and* the chip as a whole did not get any hotter, because every device sipped less power as it shrank. Designers could simply spend the extra transistors and crank the clock higher, generation after generation, and the thermal budget never sent a bill. You got speed, density, and efficiency in one bundle — and crucially, you did not have to *redesign* anything clever to collect it. You just waited for the next node.
Why the lunch ended (the power wall)
Dennard scaling rested on one quiet assumption: that you could keep dropping the supply voltage in lockstep with the dimensions. Around 2005–2006, the voltage simply refused to fall any further. A transistor needs a meaningful gap between 'off' and 'on'; push the supply too low and an 'off' transistor leaks current anyway, like a tap that never fully closes. Leakage stops being a rounding error and starts to dominate. So voltage flattened out — and the moment it did, the bookkeeping that kept power-per-area constant fell apart.
The consequence is the power wall. Transistors kept shrinking (Moore kept delivering), but now each one no longer got proportionally more efficient, so cramming more of them into the same area meant more watts and more heat in that area. You can only pull so much heat out of a chip before it cooks. By the mid-2000s, clock speeds — which had screamed upward for twenty years — hit a ceiling and have barely moved since, hovering in the few-gigahertz range. The free speed was gone.
~1985 ----------------- 2006 ----------------- today Transistors/chip doubling ........ doubling ........ doubling* (Moore: alive) Clock frequency climbing ........ PLATEAU ......... ~flat (the wall) Power per transistor falling ...... STALLS ......... ~flat (Dennard: dead) Chip heat budget easy ............ TIGHT ........... the hard limit * still doubling, but slower and far more expensive per step
With more speed off the table, the industry turned sideways: if one core cannot go faster, ship more cores. That is the multicore turn of the mid-2000s — your phone and laptop have many cores precisely because no single one could keep climbing. But that pivot exposed an even nastier truth. As transistors pile up faster than the power budget grows, you can no longer afford to switch them all on at once. The fraction you must leave dark at any moment is dark silicon — transistors you own, paid for, and cannot light up together. The power wall didn't just stop the clock; it changed what a chip is allowed to do.
What "a node" name means today
You will hear chips described by a node name — '7nm', '5nm', '3nm', '2nm' — and it is tempting to picture something on the chip that is actually that many nanometres wide. There isn't. Decades ago, the node number roughly tracked the gate length of a transistor, so the label meant something physical. That link snapped years ago. Today a '3nm' node has *no single feature* measuring three nanometres; gate lengths are still many times larger than the label.
So what is the number? Today it is essentially a marketing label — a brand for a whole generation of manufacturing, meant to signal 'denser and better than the last one.' Worse, the labels are not comparable across companies: one foundry's '3nm' and another's are different recipes with different densities, named to compete, not to measure. The honest way to compare nodes is by what they actually deliver — transistor density, speed, and power — not by the marketing nanometre.
Cost: the other wall
There was a *third* gift bundled with the old free lunch, and it may be the one we miss most: every new node used to make each transistor cheaper. More transistors per wafer, same-ish wafer cost, so cost-per-transistor fell generation after generation. That is what made 'just wait for the next node' a winning business strategy as well as a technical one.
At the leading edge, that curve has flattened — and for many designs it has stopped falling altogether. The machines and masks needed to print the most advanced nodes (extreme-ultraviolet lithography, ever-more-complex patterning) are staggeringly expensive, and designing a single chip on a bleeding-edge node now runs into the hundreds of millions of dollars. You still get *more* transistors, but each one no longer reliably gets *cheaper*. For the first time, a team can rationally choose an older, cheaper node on purpose.
The menu of escapes
So the easy scaling is over. Dennard scaling is dead (the power wall), Moore's law is slowing and getting expensive (the cost wall), and the node number stopped meaning anything physical. None of that means progress stopped — it means progress stopped being *free*. Every gain now has to be *engineered*, deliberately, against a specific limit. The rest of this track is exactly that: a menu of escapes, each one a clever answer to a wall we just named.
- Reshape the transistor itself — from flat planar devices to 3D fins (FinFET), then to gate-all-around nanosheets, and someday stacked CFETs — to keep leakage in check and density climbing.
- Print finer with better light — extreme-ultraviolet lithography (EUV) and its high-NA successor — so the smallest features can be drawn at all without absurd workarounds.
- Fix the wires, not just the switches — because shrunken interconnect now limits speed and power; moving power delivery to the back of the wafer (backside power) frees the front for signals.
- Stack in the third dimension — bond dies on top of one another with through-silicon vias and hybrid bonding to put memory and logic close, attacking the bandwidth (memory) wall.
- Split and recombine — break a big design into chiplets joined over an open die-to-die standard, mixing nodes and improving yield instead of betting everything on one giant die.
- Stop being general — design silicon specialized for one job (the domain-specific architectures behind modern AI accelerators), getting more work per watt than any general-purpose core can.
Notice the pattern: each escape answers a *specific* limit you can already name. That is the lens for the whole track. Before you learn *what* a technique does, ask *which wall* it was invented to climb. Keep that question in hand and the frontier stops looking like a grab-bag of buzzwords and starts looking like what it is — a series of deliberate, hard-won answers to the day the free lunch ended.