JOVANA
Library Glossary Getting Started Three Levels Fields How it works Mission
Join the mission
All guides

PLLs & Clock Generation

Every chip runs on a heartbeat — a clock — but the crystal you can afford is slow, a little noisy, and rarely the exact frequency your logic wants. A phase-locked loop is the circuit that takes that humble reference and grows it into a fast, clean, on-frequency clock. This guide shows you the PLL as what it really is: a feedback loop that works not on voltage, but on phase. By the end, the loop filter, charge pump, and VCO will stop being a mysterious block diagram and start being a story you can tell.

Making a clean clock

Almost every digital chip you have ever met marches to a clock — a steady square wave that says *now*, over and over, billions of times a second. The trouble is where that *now* comes from. A quartz crystal is cheap, stable, and accurate, but it only oscillates at a low frequency — often tens of megahertz. Your CPU wants gigahertz; your USB block wants something else again; your camera interface wants a third number entirely. You cannot just buy a 3 GHz crystal off the shelf, and you would not want a dozen crystals scattered across the board.

So the job is multiplication: take one slow, trustworthy reference and produce a fast clock that is locked to it — same long-term accuracy, but at a frequency you choose. Think of the crystal as a grandfather clock in the hallway, slow and reliable, and the PLL as a fast wristwatch that constantly nudges itself to stay in step with the grandfather clock. The wristwatch ticks far faster, yet over an hour it never drifts, because it keeps checking back against the slow, honest reference.

The voltage-controlled oscillator

At the heart of every PLL is an oscillator whose speed you can *steer* with a voltage. That is the VCO: feed it a low control voltage and it oscillates slowly; raise the voltage and it speeds up. It is the gas pedal of the loop — one knob that sets the output frequency.

How does a circuit turn a voltage into a frequency? The most common on-chip trick is a ring oscillator: a chain of inverters wired in a loop, with an odd number of stages so the loop can never settle and is forced to keep flipping. Each inverter takes a little time to charge and discharge the next stage's capacitance, and that delay sets the period. The control voltage simply adjusts how much current each stage gets to drive that capacitance — more current means faster charging, shorter delay, higher frequency. An LC oscillator (an inductor and a voltage-tuned capacitor) does the same job with far less jitter, which is why it is preferred for the most demanding clocks.

* VCO behaviour, idealized as a linear tuning law:
*   f_out = f_0 + K_vco * V_ctrl
*   K_vco = VCO gain, in Hz per volt (the "sensitivity" of the gas pedal)
*
* The loop actually cares about PHASE, the integral of frequency:
*   phase(t) = 2*pi * integral( f_out dt )
* -> a VCO is an INTEGRATOR from control voltage to output phase.
The VCO converts a control voltage into a frequency — but because phase is the running total of frequency, from the loop's point of view the VCO integrates. That hidden integration matters when we count poles later.

Locking a loop: the PLL

Here is the whole idea in one sentence: a PLL is negative feedback applied to phase instead of voltage. If you have read the feedback guide, everything transfers — you are just comparing a different quantity. Instead of "compare the output voltage to a reference and correct the difference," the PLL says "compare the output *phase* to the reference phase and correct the difference."

The loop is a ring of five blocks: a phase detector that measures how far apart the two clocks are, a charge pump and loop filter that turn that measurement into a smooth control voltage, the [[voltage-controlled-oscillator|VCO]] that turns voltage into a fast clock, and a ÷N divider that slows the VCO's output back down so it can be fairly compared against the slow reference. That divider is the secret to multiplication. The feedback only forces the *divided* clock to match the reference; so the full-speed VCO output ends up running N times faster.

* In lock, the divided clock equals the reference, in both frequency and phase:
*   f_out / N = f_ref      ->      f_out = N * f_ref
*
* Example: a 50 MHz crystal, divider N = 24
*   f_out = 24 * 50 MHz = 1.2 GHz
* Change N (in a register) and you re-tune the chip's clock with no new hardware.
Locked output frequency is just the reference times the divider value. Programmable N is why one PLL can synthesize a whole family of clock rates.

Phase detector, pump & filter

Walk the correction path slowly, because this is where PLLs are won or lost. The phase-frequency detector (PFD) compares the reference edge with the divided VCO edge and fires one of two outputs: *UP* if the VCO is lagging (too slow), *DOWN* if it is leading (too fast). The width of those pulses encodes exactly how far out of step the clocks are.

Those digital UP/DOWN pulses then drive a charge pump: UP dumps a packet of charge onto a capacitor, DOWN removes a packet. The capacitor is the loop's memory — its voltage is the running tally of every correction, and that voltage is exactly the VCO's control knob. This is the loop filter. Its job is to smooth the staccato charge packets into a calm DC-ish voltage, because any ripple left on that line gets multiplied by K_vco straight into jitter.

  1. The reference edge and the divided-VCO edge arrive at the phase-frequency detector; whichever is early/late sets an UP or DOWN pulse whose width is the phase error.
  2. The charge pump converts those pulses into charge added to or removed from the loop filter capacitor.
  3. The loop filter (a capacitor plus a small resistor, sometimes more) integrates that charge into a slowly varying control voltage and smooths away the per-cycle ripple.
  4. The VCO turns that control voltage into a frequency; the divider scales it down and feeds it back, closing the loop so the phase error is driven toward zero.

Jitter: time-domain noise

In an amplifier, noise shows up as unwanted *voltage* wobbling on top of your signal. In a clock, the signal *is* the timing of the edges — so noise shows up as edges arriving a little early or a little late. That timing uncertainty is [[jitter|jitter]], and it is simply the time-domain face of the same physical noise — thermal and flicker — you met in the noise guide. Jitter is to a clock what voltage noise is to an analog signal: the floor you cannot wish away, only manage.

Picture a metronome that is supposed to tick exactly every second but actually ticks at 0.998, 1.003, 0.999 seconds. The average is perfect, yet no single tick is trustworthy. For a data link, a late edge can sample a bit at the wrong moment and flip a 0 into a 1; jitter directly eats into your timing budget and caps how fast the link can run.

* .tran simulation is how jitter is actually measured in SPICE:
.tran 1p 2u            ; 1 ps step, 2 us window
* Capture each clock edge's crossing time, then post-process:
*   period jitter   = stdev of (T_k - T_{k-1})      cycle-to-cycle variation
*   RMS jitter      = stdev of edge times vs an ideal grid
* Or view it in the frequency domain with a phase-noise (.ac/.noise) run,
* where the SAME noise appears as dBc/Hz skirts beside the carrier.
Jitter (time domain) and phase noise (frequency domain) are two views of one phenomenon. A long transient measures the spread of edge times; a noise analysis shows the same energy as a skirt around the clock frequency.

Where PLLs live

Once you can see the pattern, PLLs are everywhere. Every modern SoC has a handful: one multiplies the crystal up to the CPU's clock, others spin up clocks for memory, USB, PCIe, display, and radio — each block wanting its own rate, all derived from the same honest reference. Change a divider register and the same silicon retunes to a new frequency, which is how a phone scales its clock up under load and down to save battery.

PLLs do more than multiply. With a feedback divider *and* an input divider you get a fractional frequency synthesizer — the heart of every radio, hopping to whatever channel you need. Drop the VCO and feed in incoming data instead, and the same loop becomes a clock-and-data-recovery circuit that extracts the hidden clock from a serial stream. And a delay-locked loop (DLL) is the close cousin that aligns phase using a delay line instead of an oscillator. Same principle each time: a loop that locks onto phase.