Why analog layout is artisanal
In the physical-design track you watched a tool place and wire a million CMOS gates while you mostly steered. Digital layout can be automated because a logic gate only has to be *correct* — a wire can be a little longer, a transistor a little wider, and the 0 stays a 0. Analog has no such cushion. There is no clean 0/1 to snap back to; every voltage and current is continuous, and the circuit's behavior leans on tiny differences between supposedly identical devices. That is why analog layout is still done largely by hand, one carefully drawn shape at a time.
Think of it this way. In digital, layout is *transcription* — turn the netlist into geometry and the meaning is preserved. In analog, layout is *part of the design itself*. A differential pair that is perfect in the schematic can fail in silicon purely because the two transistors were drawn facing different directions, or one sat closer to a hot power transistor than the other. The schematic captures intent; the layout decides whether physics honors it. Two layouts of the same netlist can have wildly different offset, noise, and gain.
This guide bookends the place-and-route flow from the physical-design track. The skills are cousins — both are about turning a circuit into geometry on silicon — but the priorities invert. Digital optimizes for area, speed, and routability across millions of cells. Analog optimizes for matching, symmetry, and freedom from parasitics and noise across a few dozen exquisitely sensitive devices. The same parasitic extraction step that backs up digital signoff is, in analog, where you discover whether your hand-drawn craft survived contact with reality.
Matching: identical by construction
A huge fraction of analog correctness rests on one idea: two devices behaving identically. A current mirror copies a current only as faithfully as its two MOSFETs match. A differential pair rejects common-mode noise only as well as its two halves are twins. But no two physically separate transistors are ever truly identical — etch steps vary across the wafer, doping drifts, oxide thickness wanders by fractions of a nanometer. Those random differences show up as mismatch: a stubborn input offset voltage, or a current copy that is 2% off.
Here is the single most important quantitative fact in analog layout: random mismatch shrinks as devices get bigger. Averaged over more area, the random local variations partly cancel. The standard model (Pelgrom's law) says the standard deviation of mismatch is inversely proportional to the square root of the device's gate area:
# Pelgrom mismatch model — random Vth mismatch vs device area sigma(dVth) = A_Vth / sqrt(W * L) # A_Vth ~ a few mV*um per node # Doubling BOTH W and L (4x the area) halves the mismatch sigma: sigma2 / sigma1 = sqrt( (W*L) / (4*W*L) ) = 1/2
Common-centroid & dummies
Random mismatch you fight with area. Systematic mismatch — the smooth gradients in temperature, oxide thickness, or mechanical stress that run across the die — you fight with *geometry*. The trick is the common-centroid layout: instead of placing matched device A on the left and device B on the right (so any left-to-right gradient hits them unequally), you split each device into pieces and interleave them so both share the exact same center of mass. The classic pattern for a differential pair of transistors A and B is to split each into two and lay them in a cross-coupled, ABBA / BAAB checkerboard around a common center — a linear gradient then adds the same amount to A's average as to B's, so the *difference* the circuit actually amplifies stays clean. It is the layout equivalent of two runners sharing one lane so a headwind slows them both equally.
# Common-centroid 2x2 array: A and B share one centroid # col1 col2 # [ A ][ B ] <- a linear left->right gradient g adds: # [ B ][ A ] A_total = A + (0) + A + (g) ~ B_total: difference cancels # # vs. a NON-centroid layout [A][A][B][B], where B sees the full gradient g # and a fixed A->B offset survives.
Two more habits make this real. First, dummy devices: the transistors at the *edge* of an array etch differently from those in the interior (a neighbor on one side only), so you ring the matched array with non-functional dummy copies. The dummies take the edge abuse; every device that actually matters now sees identical interior surroundings. Second, route symmetrically — the two sides of a matched pair should have the same wire lengths and the same parasitic loading, or you reintroduce by metal the very mismatch you just cancelled in diffusion.
Parasitics bite harder
Every wire you draw is secretly a resistor and a capacitor — its parasitic R and C. In digital this mostly costs a little delay. In analog the same stray R and C can move a pole, drop your gain, or detune a filter, because analog cares about *exact* values, not just whether a node eventually settles to a 1. A 20 fF parasitic on a high-impedance node that you forgot to draw is not rounding error here — it is a different circuit. Parasitics hurt analog through three doors. Gain: a single-stage amplifier's gain is set by the transconductance and output resistance, gain = -gm*ro, and any parasitic resistance in series or conductance to ground *lowers* the effective ro and steals gain. Bandwidth: extra parasitic capacitance on a high-impedance node lowers the pole frequency f = 1/(2*pi*R*C), narrowing your bandwidth and possibly hurting stability. Matching: as noted, asymmetric routing parasitics quietly unmatch a pair you worked hard to match.
* AC sweep AFTER parasitic extraction to see the real bandwidth .include amp_extracted.spice ; netlist + R/C parasitics from layout .ac dec 100 1 1G ; 1 Hz -> 1 GHz, 100 pts/decade .print ac vdb(out) vp(out) ; gain in dB and phase .end * If the post-layout pole moved in, a parasitic C is the usual culprit.
The discipline that follows is *layout-aware design*: keep wires on sensitive, high-impedance nodes short and narrow on capacitance, fat on current-carrying ones; place the devices that talk to a critical node right next to it; and treat the final parasitic extraction not as a checkbox but as the real test. The honest analog workflow is to simulate the schematic, draw the layout, *extract*, then re-simulate the extracted netlist — and only believe the second number.
Noise, shielding & the substrate
Analog spends its whole life near the noise floor, so the layout must keep externally-injected noise *out* of quiet nodes. There is the irreducible thermal noise of the devices themselves (4kTR — physics, unbeatable by layout). But on top of that sits coupled noise that good layout can largely defeat: a fast clock edge capacitively kicking a nearby analog wire, or — the sneakiest one — noise traveling through the shared substrate, the common slab of silicon every transistor sits in.
Three tools handle coupled noise. Shielding: run a grounded metal line beside or over a sensitive wire so stray capacitance couples into ground instead of your signal. Separation: keep noisy, fast-switching nets physically away from quiet, high-impedance ones — distance is cheap insurance. Guard rings: surround a sensitive block with a ring of substrate/well contacts tied to a clean supply, giving substrate noise a low-resistance path to ground *before* it reaches your circuit. Picture a moat dug around the quiet block.
Two more habits matter. Decoupling capacitors placed right at the analog supply pins give fast current surges a local reservoir so the supply rail stays quiet — the same idea as the power-grid decap from the physical-design track, but tuned for analog quiet rather than digital current. And keep the sensitive node small: less wire means less antenna for noise to couple onto, which is one more reason analog routing is drawn, not auto-generated.
The analog/digital boundary
A modern mixed-signal chip has both worlds on one die: quiet analog (your op-amps, references, converters) sitting next to a roaring digital block that switches millions of CMOS gates on every clock edge. The single most consequential floorplanning decision is where you draw the border between them — because, as we just saw, digital switching noise wants nothing more than to wander through the substrate and the supplies into your most sensitive analog node.
- Physically separate the two domains. Cluster all analog together in one region of the floorplan and all digital in another; do not interleave them. Distance plus substrate resistance is your first and cheapest filter.
- Split the supplies. Give analog its own AVDD/AGND and digital its own DVDD/DGND, joining them at a single, deliberate star point — never let noisy digital ground current flow through analog ground.
- Wall off with guard rings. Ring the analog island with substrate/well contacts to a clean ground so substrate noise drains away before it crosses the border.
- Cross the boundary deliberately. Route the few signals that must cross (the converter's digital outputs, the clock) on shielded or well-spaced wires, and keep fast digital edges away from analog inputs.
- Re-extract across the boundary. Run parasitic extraction over the whole mixed-signal region and re-simulate — coupling that no schematic showed only appears in the extracted layout.
That boundary is exactly where this analog track shakes hands with the physical-design (ic-backend) track: the digital side is placed, clocked, and routed by the automated place-and-route flow you already learned, while the analog island next door is hand-drawn with everything in this guide. A great mixed-signal chip is two crafts cooperating across one carefully guarded fence.