Data Converters: ADC & DAC

The bridge between worlds

Everything you've built in the analog rungs so far — the op-amp, the differential pair, the bandgap reference — lives in a world where voltage is a smooth, continuous quantity. It can sit at 0.5 V, or 0.5001 V, or any of the infinitely many values in between, and it drifts with temperature and shivers with noise. The digital world from the RTL ladder is the exact opposite: it knows only crisp, countable numbers — a bus is `1010_1101` and nothing fuzzier. A microphone, a temperature sensor, a radio antenna all produce the smooth kind; a processor can only chew on the crisp kind. Something has to translate between them, and that translator is the data converter.

The translation runs both directions. An ADC (analog-to-digital converter) reads a continuous voltage and reports the nearest number — it's the chip's *senses*, the way it perceives the outside world. A DAC (digital-to-analog converter) does the reverse — it takes a number and produces the matching voltage — it's the chip's *voice*, the way it acts back on the world to drive a speaker, an antenna, or a motor. Almost every interesting chip has both: it senses with ADCs, computes in digital, and speaks back through DACs.

Sampling: time goes discrete

A real signal is defined at *every* instant — there's a voltage at 1.0000 seconds, at 1.0001, at every sliver in between. A computer can't store infinitely many instants, so the first thing an ADC does is [[sampling|sample]]: glance at the input on a regular clock tick and freeze that one value, ignoring everything between ticks. Picture a strobe light in a dark room — you don't see continuous motion, you see a snapshot each flash. The flash rate is the sampling rate, `fs`, and the gap between flashes is the sampling period `Ts = 1/fs`.

Here's the part that surprises everyone: if you flash too slowly, the snapshots don't just lose detail — they actively *lie*. A fast wheel filmed at a slow frame rate appears to spin backward or stand still; that's the same effect, called aliasing. A signal frequency too high for your sample rate masquerades as a *lower* frequency that was never there, and once that fake low tone is in your samples, no amount of cleverness can remove it. The rule that keeps you honest is Nyquist: you must sample faster than twice the highest frequency present in the signal.

fs > 2 * f_max     ; Nyquist criterion — else high tones alias
; CD audio: hearing tops out ~20 kHz  ->  fs = 44.1 kHz (> 2*20 kHz)

Quantization: amplitude goes discrete

Sampling chopped *time* into discrete instants, but each frozen snapshot is still a smooth analog voltage — and we promised the digital side only crisp numbers. So the second step is [[quantization|quantization]]: round each sampled voltage to the nearest value on a fixed ladder of allowed levels. Think of measuring your height with a ruler marked only in whole centimeters — you're 173-point-something, but you must write down `173`. The leftover fraction you threw away is the price of using a finite ruler.

With `N` bits the ladder has `2^N` rungs, evenly spaced across the full-scale input range. The spacing between adjacent rungs is one LSB (least-significant bit), the smallest difference the converter can resolve: `LSB = FS / 2^N`. Every real input lands somewhere *between* two rungs, so the converter rounds — and the rounding error is at most half an LSB in either direction. That error is unavoidable; it's the fundamental cost of forcing a continuous value onto a discrete ladder.

V_LSB = FS / 2^N          ; one step of the ladder
; e.g. FS = 1.0 V, N = 12  ->  V_LSB = 1.0 / 4096 ≈ 244 uV
error_max = ± V_LSB / 2    ; worst-case rounding, ≈ ±122 uV

Resolution, bits & SNR

Treat the quantization rounding as noise and a clean relationship falls out. The signal can swing across the whole full-scale range, while the noise is stuck at roughly half an LSB — so every bit you add halves the noise step, doubling the signal-to-noise ratio, which is one extra bit ≈ 6 dB of SNR. Spell that out for a full-scale sine wave and you get the single most-quoted formula in data-converter design.

SNR ≈ 6.02 * N + 1.76   (dB)   ; ideal full-scale sine, N-bit quantizer
; N = 8   ->  ~50 dB
; N = 12  ->  ~74 dB
; N = 16  ->  ~98 dB

That formula is the *ideal*. Real converters never quite reach it, because the same enemies you fought all the way up the analog ladder show up here too — thermal noise from the resistors and switches, 1/f noise, comparator offsets, and timing wobble. Clock jitter is especially nasty for fast inputs: if your sample instant trembles, you sample the steep part of a high-frequency wave at slightly the wrong moment and read the wrong value — an error that grows with input frequency. So engineers quote ENOB (effective number of bits): take the *measured* SNR, run the formula backward, and see how many 'real' bits you actually got. A 16-bit part delivering 90 dB has an ENOB near 14.6 — those missing bits were eaten by noise.

DAC: numbers back to volts

A DAC runs the whole story in reverse: hand it a number, it produces the matching voltage. Conceptually it's a weighted sum — each bit controls a 'portion' of the output, and the portions are sized in powers of two so they add up to the right level. The most-significant bit contributes half of full-scale, the next bit a quarter, the next an eighth, and so on down to the LSB.

1. Receive the digital code, e.g. the 4-bit word 1011.
2. Each bit switches its weighted contribution on or off: bit3 = 1/2 FS, bit2 = 1/4 FS, bit1 = 1/8 FS, bit0 = 1/16 FS.
3. Sum the enabled weights: 1011 = 1/2 + 0 + 1/8 + 1/16 = 11/16 of full scale.
4. A buffer drives that summed voltage out — usually followed by a reconstruction low-pass filter that smooths the staircase of discrete output steps back into a continuous waveform.

Those 'weights' are built from precisely matched analog elements — a binary-weighted array of capacitors or currents, or the elegant R-2R ladder that needs only two resistor values. And here every layout lesson from earlier rungs cashes in: if the weights don't match their ideal ratios, the steps come out uneven and the converter is nonlinear. That's exactly why precision converters lean on tricks like the current mirror for matched currents and common-centroid layout to cancel process gradients across the die. Matching is the whole ballgame — a 12-bit DAC needs its elements to match to better than 1 part in 4096.

A tour of ADC architectures

There's no single best ADC — only the right trade among speed, resolution, and power, the iron triangle of converter design. Three architectures cover most of the map, and knowing where each one sits tells you most of what you need.

1. Flash — fastest, hungriest. Build a wall of 2^N−1 comparators, one per ladder rung, and compare the input against all of them at once. The answer pops out in a single clock — brilliant for gigahertz-rate jobs like radio and high-speed links. But comparator count *doubles every added bit*, so flash is power-hungry and area-hungry; it's practical only at low resolution, roughly 6–8 bits.
2. SAR — the balanced workhorse. Successive-approximation does a binary search: guess the most-significant bit with an internal DAC, ask one comparator 'too high or too low?', lock that bit, then guess the next — N comparisons for N bits, like guessing a number by repeatedly halving the range. One comparator, one small DAC, modest power; medium speed and 8–18 bits. This is the default you reach for first.
3. Sigma-delta (ΣΔ) — highest resolution, narrow band. Sample *far* faster than Nyquist (oversample) and add a feedback loop that shapes the quantization noise, pushing it up out of your band where a digital filter sweeps it away — trading raw speed for astonishing resolution. 16–24 bits for audio, sensors, and instrumentation, where the signal is slow but you want every last bit of fidelity.

Notice the family resemblance to the analog circuits you already know. The SAR's heart is a comparator (a differential pair pushed to a decision) plus a DAC. The sigma-delta is, at its core, a feedback loop — and just like the op-amps from the GBW and phase-margin rungs, that loop must be stable to work. Data converters aren't a separate discipline; they're your analog building blocks assembled with purpose.