Setting the operating point
In the digital world a transistor is a switch — fully on or fully off, 0 or 1, and you never linger in between. Analog is the opposite. Here you deliberately park each MOSFET *in between*, in the steep middle of its curve, and hold it there with steady DC voltages and currents. That resting state — the quiet current flowing and the quiet voltages sitting on each terminal before any signal arrives — is the [[bias-point|operating point]], also called the Q-point (Q for quiescent, meaning *at rest*).
Think of it like balancing a seesaw before kids jump on. You first get the plank level and steady; *then* a small push at one end produces a clean, proportional response at the other. If the plank starts already slammed to the ground, no push does anything. A transistor is the same: you bias it into its responsive saturation region (gate above threshold, drain voltage high enough to keep it there), and only then will a tiny signal riding on top of that DC produce a clean, amplified output. The bias is the level plank; the signal is the gentle push.
Concretely, the operating point is just a handful of DC numbers per device: the drain current I_D, the gate-source voltage V_GS, and the overdrive V_ov = V_GS − V_th (how far you pushed the gate past the turn-on threshold). You can find them by hand from the device equations, but in practice you ask a simulator for the .op — the operating-point solution — which reports every node voltage and branch current at rest. That printout is the foundation everything else is built on.
* DC operating point: solve all node voltages & branch currents at rest .op * (simulator prints, e.g.) * M1: Id = 50uA Vgs = 0.65V Vth = 0.45V Vov = 0.20V * M1: region = saturation
Why bias matters
Here is the part newcomers underestimate: the operating point does not just *turn the circuit on* — it silently sets how good the circuit is. The single most important quantity it controls is [[transconductance|transconductance]], written gm: how strongly a small wiggle in gate voltage turns into a wiggle in drain current. More gm means more gain. And gm is set almost entirely by the bias current you chose.
The plain-language version first: push more standing current through a transistor and it becomes more sensitive — a given voltage nudge moves more current, so it amplifies harder. Now the number. For a MOSFET in saturation, a compact and famous relation is:
gm = 2 * Id / Vov ; transconductance from bias * Intrinsic gain of one transistor = gm * ro * where ro is the device's output resistance (how flat its * current-source behavior is). For a common-source stage: Av = -gm * ro ; small-signal voltage gain (sign = inverting)
So the chain of consequences is direct: bias current → gm → gain. Choose too little current and gm collapses, the stage barely amplifies, and the circuit is sluggish and noisy. But you cannot just crank the current to the sky, which brings in the second thing bias controls: headroom. Every transistor needs a minimum drain-source voltage to stay in saturation; pile up too many stacked devices, or swing the output too far, and one of them drops out of saturation. The signal then clips — flattening at the rails like a singer screaming past their range. Wrong bias, in other words, fails in two opposite ways: too little gives you no gain, too much (or badly distributed) gives you no headroom and clipping.
The current mirror
You now know the whole circuit hangs on getting clean, well-defined currents into each transistor. But how do you *deliver* a precise current — say exactly 50 µA — to a dozen places scattered across the chip, when the supply voltage drifts and the temperature swings? You make one good current once, and then copy it everywhere. The workhorse that does the copying is the [[current-mirror|current mirror]], and it is, without exaggeration, the most-used building block in all of analog IC design.
The trick rests on one fact about matched transistors: if two identical MOSFETs share the same V_GS, they carry the same drain current. So you take a reference current I_REF and force it through one transistor (M1) wired *diode-connected* — gate tied to drain. That transistor automatically develops whatever V_GS is needed to swallow exactly I_REF. Now you simply hand that same V_GS to a second, identical transistor (M2). M2 has no choice: same V_GS, same device, so it conducts the same current. M1 *reads* the current and sets the voltage; M2 *re-creates* the current from that voltage. The reference is the tuning fork; the mirror outputs hum at the same pitch.
* Simple NMOS current mirror * M1 diode-connected (gate=drain) is the 'reference' side * M2 shares the same Vgs and 'mirrors' the current IREF vdd n_gate 50u ; the reference current we want to copy M1 n_gate n_gate 0 0 nch W=2u L=0.2u ; diode-connected: G=D M2 out n_gate 0 0 nch W=2u L=0.2u ; same Vgs -> same Id ~ 50uA .op
Copying currents around
Once you can copy a current, two superpowers fall out. First: scaling. Because drain current scales with a transistor's width-to-length ratio (W/L), you do not have to copy 1:1. Make the output transistor twice as wide and it mirrors *twice* the current; make it half as wide for half. A single reference can fan out into a whole family of currents — 1×, 2×, ½× — just by sizing the mirror legs, the way one master clock can drive many gears of different sizes.
* Ratioed mirror: scale the copy by the W/L ratio * I_out / I_ref = (W/L)_out / (W/L)_ref M1 ref ref 0 0 nch W=2u L=0.2u ; reference leg (1x) M2 o2 ref 0 0 nch W=4u L=0.2u ; copies 2 x I_ref M3 o3 ref 0 0 nch W=1u L=0.2u ; copies 0.5 x I_ref
Second: the active load. A mirror's output transistor behaves like a current source, and a current source has very high output resistance (ro). Recall that a stage's gain was gm·ro — so if you replace a plain resistor load with a *mirror* acting as the load, you get an enormous effective ro in a tiny area, and the gain shoots up. This is why you will see a current mirror sitting at the top of nearly every differential pair and gain stage: it is doing double duty, both biasing the stage and serving as a high-impedance active load that a passive resistor could never match without eating the whole chip.
References & the bandgap
A mirror copies a current faithfully — but copies of *what*? Every mirror needs an original: a reference current or voltage that is genuinely stable. And here lies the deep problem. The obvious ways to make a reference all drift. Tie current to the supply with a resistor and it moves when the battery sags. Lean on a transistor's threshold or a resistor's value and both wander with temperature. You need a source of *truth* that barely cares about supply voltage or temperature — a fixed star to navigate by.
The celebrated solution is the [[bandgap-reference|bandgap reference]], and its idea is beautiful: cancel one temperature drift against an opposite one. Two natural voltages inside any silicon chip move with temperature in opposite directions. A diode's (or transistor's) base-emitter voltage falls as things heat up — call it CTAT, *Complementary To Absolute Temperature*, sliding down at roughly −2 mV per °C. Meanwhile the *difference* between two such junctions run at different current densities *rises* with temperature — call it PTAT, *Proportional To Absolute Temperature*. Each alone is useless as a reference because each drifts. But add a falling voltage to a rising voltage in just the right proportion and the slopes cancel, leaving a sum that is nearly flat.
* Bandgap: sum a falling (CTAT) and a rising (PTAT) term V_BG = V_BE + K * V_T * V_BE : base-emitter voltage, CTAT (~ -2 mV/degC) * V_T : thermal voltage kT/q, PTAT (~ +0.087 mV/degC) * K : scaling chosen so the two slopes cancel * Result: V_BG ~ 1.2 V, nearly flat over temperature
From that one stable ~1.2 V, the rest follows: drop it across a well-controlled resistor to make a stable reference *current*, then let your current mirrors copy and scale that current to every block on the chip. The bandgap is the fixed star; the mirrors are the fleet that carries its bearing everywhere.
Drift over PVT
No reference is perfect, and no bias holds dead still — because the silicon itself is a moving target. The three things that conspire against you travel under one banner: PVT — Process, Voltage, Temperature. Every analog circuit must keep working not at one tidy nominal condition, but across the whole envelope of all three, simultaneously, for years.
- Process (P): no two wafers are identical. Threshold voltages, resistor values, and transistor strengths drift from lot to lot and even across a single die. Foundries hand you corner models (slow / typical / fast) and you must verify your bias survives all of them — which is the deepest reason mirrors copy *ratios* of matched devices rather than absolute values, since ratios cancel much of the process spread.
- Voltage (V): the supply is never exactly nominal. Batteries sag, regulators ripple, and neighboring circuits yank the rail up and down. A good reference and a well-designed mirror must hold their current steady even as the supply moves — quantified as supply rejection.
- Temperature (T): a chip might run from a freezing −40 °C to a scorching +125 °C. Mobility, threshold, and junction voltages all slide with heat — which is the entire reason the bandgap exists, and why you sanity-check every bias across the temperature range, not just at room temperature.
The way you actually catch drift is by sweeping it in simulation. You do not just take one .op at nominal — you re-solve the operating point as temperature (or supply) marches across its range and watch whether your reference current and gm hold. A flat line means a robust bias; a line that droops or soars warns you the circuit will misbehave somewhere in the field.
* Sweep the bias across temperature and watch the reference current .dc temp -40 125 5 ; step temperature, -40 to +125 C .print dc i(vmeas) ; reference/bias current vs. temperature * A good bandgap-derived bias stays nearly flat across this sweep