The problem: an open-loop converter is blind
Recall the headline result from rung 4: an ideal buck converter outputs roughly Vout = D · Vin, where D is the duty cycle — the fraction of each switching period the high-side switch is on. Set Vin = 12 V, want 5 V, so D = 0.42. Fix that duty cycle forever and walk away. This is open-loop operation, and it works perfectly — for exactly one set of conditions.
Now disturb it. The battery feeding Vin drains from 12 V toward 10.5 V — your 5 V output slumps to 4.4 V. A motor downstream suddenly demands 3 A instead of 0.5 A — the extra current pulls the output down through every parasitic resistance in the path. The MOSFET heats up and its on-resistance climbs. None of these are exotic; they happen continuously in every device on your desk. Open-loop, the converter never notices and never corrects. The output simply drifts wherever physics drags it.
Closing the loop: measure, compare, correct
The cure is the same trick a thermostat uses to hold a room at 21 °C while the weather outside does whatever it likes. Don't trust your knob setting — watch the result and react to the error. We add three pieces: a way to sense the output, a stable reference to compare against, and a controller that nudges the duty cycle in whichever direction shrinks the gap. This is textbook negative feedback.
- Sense. A resistor divider scales the output down to a comfortable voltage. For a 5 V output and a 1.0 V reference, divide by 5 — feed back 1.0 V when Vout is exactly right.
- Compare. An error amplifier subtracts the fed-back voltage from the fixed reference (often a bandgap reference, rock-steady over temperature). Its output is the error signal: how wrong, and in which direction.
- Decide. A compensator (a tuned amplifier with carefully placed poles and zeros) turns that error into a control voltage — how hard to push.
- Modulate. A PWM comparator turns the control voltage into a duty cycle: it compares the control level against a sawtooth ramp and emits a high pulse for exactly as long as the control sits above the ramp.
- Drive & repeat. The pulse switches the MOSFET, the LC filter averages, and the new output loops back to step 1 — tens of thousands to millions of times per second.
Vref(1.0V) --->(+)\ +5V out
>--[ ERROR AMP / COMPENSATOR ]--+ |
Vfb ------------(-)/ | [R1]
^ v |---> Vfb (=1.0V when Vout=5V)
| [ PWM COMPARATOR ] [R2]
| | |
| sawtooth ramp /|/|/| -------------->| GND
| v
| PWM (duty = D)
| |
| [ GATE DRIVER ]
| |
| v
+----[ Vout ]----[ L ]----[ C ]<----[ MOSFET switch ]<---- Vin(12V)
(sensed) output LC filter
If Vout droops -> Vfb < 1.0V -> error grows -> control rises
-> PWM duty D increases -> more energy per cycle -> Vout climbs back. Stability: the loop can fight itself
Feedback is not free. Every element in the loop — the LC output filter especially — adds delay and phase shift. The output capacitor and inductor form a resonance that lags the signal; push a correction and it arrives late. If by the frequency where the loop's gain still exceeds 1 the total lag reaches 180°, your *negative* feedback has quietly rotated into *positive* feedback. The supply rings, or sustains a steady oscillation you can see as fuzz on the output and hear as a whine.
Engineers tame this exactly the way the control-systems track teaches: shape the loop so that where the gain crosses unity there is still comfortable margin before 180° — the phase margin, with 45–60° a healthy target. That shaping is the compensator's job, and you verify it on a Bode plot of loop gain and phase. This is the bridge from "it powers up on my bench" to "it survives a 5 A load step without ringing for 200 µs."
The gate driver: muscle for the switch
Now the part beginners always skip and engineers never can. The PWM comparator emits a clean logic pulse — maybe 0–3.3 V, able to source a few milliamps. The MOSFET it must switch wants its gate driven to perhaps 10 V and, far more importantly, wants that gate's charge moved *fast*. You cannot wire the PWM pin to the gate directly. You need a gate driver: a dedicated buffer that takes the feeble logic signal and slams the gate with amps of peak current.
Why amps, for a gate that draws no steady current? Because a power MOSFET's gate is a capacitor — its total gate charge Qg might be 20 nanocoulombs. To turn the device fully on or off in, say, 20 ns, you must shove all 20 nC through the gate in 20 ns. That is current = charge/time = 20 nC / 20 ns = 1 ampere, peak. The gate draws zero average current but a violent transient gulp at every edge. Starve it and the transition slows; a slow transition means the MOSFET spends longer in its half-on, lossy region.
Switching loss intuition — why edge speed pays the bill
--------------------------------------------------------
During a transition the FET has BOTH high V across it AND
rising/falling I through it -> instantaneous power V*I is large.
V_ds \__ __/ (drain-source voltage)
\__ __/
I_d ___/ \___ ___/ \___ (drain current)
/ \______/ \
P = V*I /\ /\ <-- loss spikes only
/ \__________________/ \ during the edges
Fast edges (big gate-drive current) -> narrow loss spikes.
Slow edges (weak drive) -> WIDE loss spikes -> heat.
Switching loss ~ f_sw x (edge energy),
so it grows with switching frequency too. Dead-time, high-side drive & the synchronous switch
Efficient modern converters replace the freewheeling diode with a second MOSFET — a synchronous rectifier — because a transistor's tiny on-resistance drop beats a diode's stubborn 0.5 V forward drop. Now you have two switches in a vertical stack between Vin and ground: high-side on top, low-side below, their midpoint feeding the inductor. They must take turns. If they are *ever* on together, even for a nanosecond, they form a dead short across the input — a destructive event called shoot-through that can vaporize both devices.
The defence is dead-time: a deliberate sliver of time — tens of nanoseconds — where the driver turns the outgoing switch fully off *before* turning the incoming one on. Both gates low, briefly, every cycle. Too little dead-time risks shoot-through; too much wastes efficiency (current limps through the body diode during the gap). Good gate-driver chips manage this for you, and the best ones sense the switch node to adapt the dead-time automatically.
Isolated vs non-isolated, and where this leads
One more architectural fork. Everything so far has been non-isolated: input and output share a ground, so charge flows in a single connected circuit. That is perfect for the point-of-load converters dotted across a circuit board, stepping 12 V down to the 1.8 V, 3.3 V, and 5 V rails the chips need. Buck, boost, and buck-boost are all non-isolated.
But a phone charger plugged into 230 V mains *must not* present a 230 V path to the 5 V USB pins a human might touch. Isolated topologies — flyback, forward, LLC — replace the inductor with a transformer, so energy crosses a magnetic gap with no direct electrical connection. The feedback signal then has to cross that same barrier, usually through an optocoupler or a tiny signal transformer, so the loop you built above gets a galvanic moat in the middle of it. Same feedback principle, extra plumbing for safety.