From pixels to a box of boards
Stand back and look at how far this rung has carried you. Guide 1 explained what a PCB physically is — FR-4 with copper layers, solder mask, and silkscreen. Guide 2 took your schematic and turned it into a layout, carrying the netlist as the contract between the two. Guides 3 and 4 gave you the physical vocabulary — traces, vias, pads, footprints — and the hard lesson that the ground plane and the loops you draw are themselves part of the circuit. You now have a beautiful layout glowing on screen. It does absolutely nothing.
Between that glowing image and a board you can hold lies a gap that trips up almost every beginner. Two things have to happen. First, the design must obey rules a real factory can build — there are widths too thin to etch, gaps too small to keep apart, holes too tiny to drill. Second, the design must be exported into a set of standard files the factory's machines actually read; nobody emails the fab your project file. This guide is about crossing that gap cleanly, so the board that arrives matches the board you drew.
Design rules and the DRC: the factory's rulebook
Every PCB factory publishes a list of what it can and cannot make, called its design rules or capabilities. The numbers are mundane but unforgiving: a minimum trace width and minimum spacing (a cheap fab might allow 0.15 mm, about 6 mil, for each), a minimum drilled hole (often 0.3 mm), a minimum annular ring — the collar of copper that must surround a hole so the drill can wander a little and still land on metal — and a minimum clearance from any copper to the board's edge. Draw a trace thinner than the fab can etch, or place two pads closer than it can keep apart, and the board either cannot be made or comes back with shorts and breaks.
Nobody checks hundreds of these by eye. Your EDA tool runs a design rule check, the DRC: you type in the fab's numbers once, and the software sweeps the whole layout flagging every violation — this trace is 0.12 mm where the minimum is 0.15, these two pads are 0.1 mm apart, this hole has too thin a ring. Think of it as an automated proofreader for manufacturability. It is tireless and literal: it will not catch a stupid design, but it will catch every clearance you fumbled. A clean DRC is the gate you must pass before exporting anything.
Closely related is design-for-manufacture, or DFM — a softer layer of advice the DRC may not enforce but the fab will thank you for. Tear-dropping a trace where it meets a pad so a slightly misregistered drill does not break it; leaving enough room between surface-mount parts for the assembly machine and for rework; not running a fine trace right at the very edge. The DRC tells you what is forbidden; DFM tells you what is wise. Both exist because the factory is a physical process with tolerances, not a perfect printer.
Copper carries current — and heat
A trace is not an ideal wire; it is a thin ribbon of copper, and copper is a resistor. Its thickness is quoted in ounces: '1 oz copper' means about 35 micrometres of copper, the most common default. That layer has a sheet resistance of roughly 0.5 milliohm per square, where a 'square' is any patch as long as it is wide. So a trace 0.25 mm wide and 50 mm long is 50/0.25 = 200 squares, giving 200 times 0.5 mΩ = 0.1 ohm. Push 1 A through it and you lose V = I times R = 0.1 V along the way, dissipating P = I^2 times R = 0.1 W as heat in the copper. On a logic signal that is nothing; on a power rail feeding an amplifier, that drooping 0.1 V can matter.
Heat sets the real limit on how much current a trace may carry. Force too many amps through too thin a ribbon and it warms up; warm copper has more resistance, which warms it more. Fab and IPC charts capture this as a rule of thumb: for 1 oz copper on an outer layer, a trace about 0.25 mm (10 mil) wide carries roughly half an amp to an amp for a gentle 10 °C rise; a 1 mm trace handles a few amps; a 5 A rail wants a wide pour, not a thin line. These are rough guides from charts, not exact laws — the safe move is to size power traces generously and let logic traces be as thin as the DRC allows.
When a part itself runs hot — a regulator, a power transistor — the copper doubles as a radiator. A wide copper pour or a whole plane under the part spreads heat sideways into the board, and a cluster of small 'thermal vias' stitches that heat down to copper on the other layers, multiplying the cooling area. For serious power you bolt on a metal heat sink, but a generous copper pour is the free first step every layout should take. Remember from guide 4 that vias also carry signal return current; here they carry heat too. The same humble plated hole does double duty.
The files the fab needs
Once the DRC is clean, you export. The factory does not want your editable project; it wants a frozen, unambiguous description of every layer. The historic universal language is the Gerber file: one file per layer, each a list of shapes — draw this trace here, flood copper there, open the solder mask over this pad. You export one Gerber for top copper, one for bottom, one each for the two solder-mask layers, one each for the silkscreens, and one for the board outline. Alongside them goes a separate drill file (the Excellon format) listing every hole's x, y position and diameter, because holes are drilled, not etched.
FILE (what the fab reads) WHAT IT DESCRIBES ------------------------------- -------------------------------- *.GTL / *.GBL (Gerber) top / bottom copper *.GTS / *.GBS (Gerber) top / bottom solder mask *.GTO / *.GBO (Gerber) top / bottom silkscreen *.GKO or edge.gbr board outline (the cut shape) *.DRL (Excellon) drill file: hole x,y + diameter bom.csv every part: ref, value, package cpl / centroid.csv x, y, rotation for pick-and-place BARE board needs : copper + mask + silk + outline + drill ASSEMBLED also : + BOM + centroid + the actual components
Two more files matter if you want the board assembled, not just bare. The bill of materials, the BOM, is a spreadsheet listing every component: its reference (R1, C7, U3), its value, and crucially its exact package — a 10 kΩ resistor in an 0603 size is a different line item from the same value in an 0805. The other is the pick-and-place or centroid file, giving the x, y, and rotation of each part so the assembly robot knows where to set it down. A surface-mount board is placed by machine from these files; a through-hole board is often still stuffed by hand.
- Run the DRC and fix every error until it is clean. Then run the electrical-rules check too, which catches unconnected nets and pins you forgot — a different kind of mistake from a clearance violation.
- Export the Gerbers and the drill file, then open them in a free Gerber viewer and look. This is the single most valuable habit: you see exactly what the fab will see, layer by layer, and catch a missing mask opening or a flipped layer before it costs you a board.
- Generate the BOM and the centroid file if you want assembly, and check each footprint's pin order and package against the part's datasheet — a wrong footprint passes the DRC perfectly and still makes the board useless.
- Zip the set, upload to the fab, choose options (board thickness, copper weight, mask colour, quantity), confirm the rendered preview, and order. Buy a few spares; the marginal cost per extra board is tiny.
When the layout becomes the component
For slow circuits, a trace is just a wire and its exact width or path barely matters electrically. But push the speed up — fast digital edges, RF, high-speed data — and a trace stops behaving like a simple wire and becomes a transmission line with a characteristic impedance set entirely by its geometry: its width, the thickness of FR-4 between it and the ground plane below, and the copper weight. Get that impedance wrong and the signal partly bounces back at each end — a reflection — smearing edges and corrupting data. The wire you drew has become a circuit element in its own right, with no symbol on the schematic.
The cure is controlled impedance, and the workflow is a neat collaboration. You tell the fab, 'this trace must be 50 ohm,' and the fab — who knows the exact thickness and dielectric of every layer in your board's stackup — tells you the precise trace width to draw, perhaps 0.3 mm above a ground plane 0.2 mm down. You draw to that width; they manufacture to that stackup; the geometry delivers the impedance. It is exactly the impedance-matching idea from earlier rungs — choosing a hose that neither chokes nor wastes the flow — now baked into the copper itself.
Getting it made — and the honest reality
A few days after you order, a box arrives: real boards, your design in copper and fibreglass, ready to solder. That moment is genuinely thrilling, and it is also where the honest reality of guide 4 comes home to roost. Your simulator could model every component perfectly and still be blind to the one thing the real board adds: itself. The decoupling caps only work if their loop is tight; the ground only stays quiet if the return paths are short; the fast trace only behaves if its impedance is right. None of that is in the schematic. On a real board, the layout is a circuit element — invisible on paper, decisive in copper.
Which is why no professional expects the first spin to be perfect. You build it, you find the two things you got wrong — a swapped footprint, a missing decoupling cap, a ground return that hums — and you fix them on the next revision. This is healthy design iteration, not failure: the cheap, fast way to learn what a layout really does is to make one, poke it with the bench tools from the instruments rung, and revise. A working reference design and a careful first prototype save you far more spins than any amount of staring at the screen.