The Ground Plane and Layout as a Circuit

On paper a wire is a wire; on copper it is a circuit

By now you can picture the board as stacked copper layers, and you can place traces, vias, pads, and footprints from the earlier guides in this rung. The schematic that fed all that drew an ideal world: a wire is a perfect zero-ohm, zero-delay connection, and a ground symbol is one tidy point. Copper is not that generous. Every centimetre of trace is a tiny resistor in series and — far more importantly once signals move fast — a tiny inductor. Nobody drew those parts, yet they are soldered into your board for free. That is the one idea this guide turns over and over: the layout is itself a circuit, stuffed with parasitic components you did not choose but must still live with.

How big are these stray parts? A handy rule of thumb: a typical signal trace carries roughly 1 nH of inductance per millimetre of length (the exact value depends on width and how far it sits above its return, so read 0.5 to 1 nH/mm as the right ballpark), and a via adds about another nanohenry. That sounds laughably small — until something changes fast. The voltage across an inductor is V = L times (di/dt); it fights changes in current. So a current that swings 0.1 A in 1 ns has di/dt = 0.1 / 10^-9 = 10^8 A/s, and just 10 nH of trace — about a 10 mm hop — develops V = 10 x 10^-9 times 10^8 = 1 V across it. A full volt of glitch, conjured out of a wire you were sure was a dead short.

Every current makes a round trip — and the ground plane gives it one

The deepest habit to build in layout is this: current never flows one way. By Kirchhoff's current law, every electron that leaves a source down a signal trace must find its way back. The forgotten half of every connection is the return path. On the schematic all those returns collapse into one neat symbol — ground — and it looks like a single, perfect node. On the board that "single node" is real copper with real impedance, and the return current is every bit as physical as the signal, threading its own way home.

The cleanest way to give every return an easy road home is a ground plane: one whole copper layer left as an unbroken sea of ground, sitting directly under your signal layer (exactly why guide 1 fussed over the layer stack-up). Now no return has to hunt for a skinny trace — it has an ocean of copper. Here is the part that surprises every newcomer: at high frequency the return does NOT spread out and take the short straight line back. It hugs the plane right beneath the signal trace, mirroring its path step for step. Why? Because that route encloses the smallest possible loop, and fast current always chooses the path of least inductance, not least resistance.

 GOOD: solid ground plane under the signal

   top    >---[========= signal trace =========]--->
   plane  <---[======== return current ========]---<
              return mirrors the trace  =  tiny loop


 BAD: a slot cut in the plane (a via row or split)

   top    >---[===== signal trace =====]------------>
   plane  <--[==== return ====]  SLOT  [=== ? ===]--<
                              \___ detour ___/
              return must go AROUND  =  big loop
              =  ringing, radiation, crosstalk

That is the quiet superpower of a solid plane: it makes a tiny return loop automatically, with no thought from you, for every trace on the board at once. But the instant you cut a slot in it — a careless row of vias, a routing channel, a split between sections — any return that needs to cross is forced to detour around the gap. The loop balloons, the inductance shoots up, and the trace crossing the gap turns into a little antenna that both radiates and picks up noise. The rule writes itself: never break the ground plane underneath a fast signal.

Loop area is the master variable

Why obsess over the size of that loop? Because loop area is the single number that governs three different troubles at once. A current loop is a one-turn coil, and its inductance grows with the area it encloses. A bigger loop (1) stores more energy in its magnetic field, so it rings harder and develops more of that L times di/dt glitching we just met; (2) radiates that changing field more strongly, turning your board into a little transmitter — bad for electromagnetic compatibility; and (3) catches more of the outside world's changing fields, the inductive coupling that lets one circuit's noise jump into another's loop. Shrink the loop and all three improve together. Half the craft of good layout is, quite literally, keeping loops small.

The same loops are how neighbouring traces gossip behind your back. When a fast signal's loop sits close to another trace's loop, their magnetic and electric fields couple and a ghost of one shows up on the other — crosstalk. A ground plane fights this too: by pulling every return tight under its own trace, it keeps each loop small and private, so adjacent signals share far less field with each other. Run a quiet plane (or even a single grounded "guard" trace) between two sensitive lines and you give their fields a place to terminate that is not each other.

Decoupling: the local water tank, placed where it counts

You met the decoupling capacitor back in the noise rung as the local water tank beside a thirsty machine: when a chip suddenly gulps current, the long thin pipe from the power supply sags, and the local tank tops it up so the chip's own supply rail never droops. On a PCB that idea becomes a placement problem, and here placement beats value. The cap only helps if the loop from cap to the chip's power pin, through the chip, out the ground pin, and back to the cap is tiny — because that loop's own inductance is exactly what limits how fast the tank can pour.

Put numbers on it. Suppose a logic chip draws a 0.1 A spike in 1 ns. If the cap sits 10 mm away through skinny traces — call it 8 nH of loop inductance — the supply rail dips by V = L times di/dt = 8 x 10^-9 times 10^8 = 0.8 V. On a 3.3 V part that is a brown-out the chip may read as garbage and reset at random. Move the same cap to 1 mm away, with short fat traces and a via from each pad straight into the planes — perhaps 1 nH — and the identical spike dips the rail only 0.1 V. Same capacitor, eight times better, purely from where you put it. That is why a 100 nF cap belongs jammed right against the chip's power pin, not parked "somewhere on the board".

1. Put the cap as close as physically possible to the chip's power-and-ground pin pair — millimetres, not centimetres. Closeness is the whole game.
2. Use short, fat traces from the cap's pads, and drop a via from each pad straight into the power and ground planes, so the supply loop is as small as the copper allows.
3. Give each cap its own short path to the plane; do not daisy-chain several caps along one long shared trace, which adds inductance to all of them.
4. Match value to speed: a bulk cap (say 10 uF) handles slow, large demands while a small 100 nF handles the fast edges — and place the small fast one closest. Honest caveat: above its self-resonant frequency a cap stops looking capacitive and turns inductive, so it is the loop inductance, not the printed capacitance, that sets the real high-frequency limit.

One ground, but not one wire: partitioning the returns

A ground symbol promises that every point on it sits at exactly 0 V. Copper breaks that promise. Push a noisy return current through the resistance and inductance of a shared stretch of ground copper and the far end is no longer at 0 V relative to the near end — it bounces. If a sensitive analog stage shares that same copper with a busy digital stage, the digital return's wiggle rides straight into the analog stage's reference, corrupting the very zero it measures against. This is the shared-impedance ground loop from the noise rung, now made of copper.

The cure is to keep noisy and quiet return currents from sharing the same stretch of copper. Star grounding routes each stage's return separately back to one common point, so no stage's current ever flows through another's path. On a plane the gentler version is to partition: let the analog section keep its own quiet region of the plane and the digital its own, joined by a single bridge near the supply or the data converter, so digital return current never has to cross the analog region to get home. Honest caveat — partitioning is a scalpel, not a hammer. A slot in the plane in the wrong place forces a fast return to detour and creates the very loop you were trying to avoid, which is often worse than leaving the plane whole. For most boards, one unbroken plane plus careful component placement beats a cleverly chopped-up one.