Two drawings of one circuit
Every circuit you have met so far lived as a schematic — a clean logical drawing where a resistor symbol can sit anywhere, two crossing wires do not touch, and the only things that matter are what connects to what and each part's value. The previous guide showed the other half of the story: the physical printed circuit board, an FR-4 sandwich with copper layers, solder mask, and silkscreen. This guide marries the two. Your design tool (an EDA package such as KiCad, Eagle, or Altium) has two linked editors for exactly this: schematic capture, where you draw the logic, and PCB layout, where you place that logic onto real copper.
The difference between the two is the whole game. The schematic is freed from geometry — it cares about connectivity, not distance, so you arrange it for human readability. The layout is bound by physics — every component occupies real space, and every connection becomes a copper line of real length, real width, and a real path back. A circuit can be flawless on the schematic and yet fail completely on the board, because the layout adds things the schematic never showed. Crossing from one drawing to the other is where electronics stops being abstract.
The netlist: the contract between two worlds
When you finish the schematic, the tool reads it and extracts a netlist — a plain, machine-readable list of every electrical connection. The key word is net: a net is one electrically common node, the set of all pins that should sit at the same voltage and be joined by copper. (You already know this idea as a node from the nodal-analysis rung; the netlist is just that idea written down for the whole board.) For each net the file lists exactly which component pins belong to it. That list is the contract the layout must honour.
SCHEMATIC NETLIST LAYOUT symbols + values ----> nets bind pins ----> footprints + copper --------------------------------------------------------------------------- net name the pins that must end up electrically common -------- --------------------------------------------- +5V U1-8 C1-1 R1-1 GND U1-4 C1-2 J1-2 OUT U1-1 R1-2 J1-1
But a netlist of pins is not yet placeable — the tool needs to know how big each part physically is. So every schematic symbol must be paired with a footprint: the exact pattern of copper pads (the little landing zones where a part's leads solder down) plus the part's outline and hole positions. The same 10k resistor symbol could map to a fingernail-sized through-hole part or a speck-sized surface-mount chip — identical on the schematic, wildly different in copper. You get the right footprint from the part's datasheet, and getting it wrong gives you a board no real component will fit onto.
Placement first, then routing
Now you push the netlist into the layout editor and a pile of footprints appears, tangled in a web of thin straight lines called the ratsnest (鼠線). Each line is a connection the netlist demands but that no copper has satisfied yet — your to-do list, drawn in air. From here the work splits cleanly into two stages, and the order is sacred: placement (deciding where every footprint sits) comes first, then routing (drawing the actual copper). Good placement makes routing almost draw itself; bad placement makes it impossible no matter how clever you are.
- Place by function. Group the design into blocks — power in, analog, digital — and keep the parts of one signal path together so signals flow across the board in a sensible direction. Watch the ratsnest: nudge parts until its lines stop crossing and become short. Crossings you do not untangle now become vias you must drill later.
- Pin down the fixed parts. Connectors, mounting holes, and anything that must align with an enclosure go to their exact required spots first — everything else then arranges around them, not the other way round.
- Put each decoupling capacitor hard against its chip's power pin, before you route anything. This is non-negotiable and is why placement leads routing — the copper distance here directly costs performance.
- Only now route. Draw copper net by net — power and ground first, then the touchy signals, then the rest — sizing each trace's width to the current it carries. Re-run the ratsnest check until every line has become real copper and nothing is left dangling.
Two big families of parts shape how you place. Through-hole components have wire leads that poke through drilled holes and solder on the far side — sturdy, forgiving to hand-solder, but bulky and occupying both faces. Surface-mount parts sit flat on pads on one surface — tiny, dense, placed by machine, and the backbone of nearly every modern board. Most real designs are mostly surface-mount with a few through-hole parts for connectors and power, and that mix decides how tightly you can pack the board.
The layout is itself a circuit
Here is the honest heart of PCB design, the idea everything else in this rung circles. On the schematic a wire is an ideal: zero resistance, zero length, perfect and invisible. On the board a trace is real copper — it has a little resistance, it has inductance, and two traces running close together have capacitance between them. These parasitics never appear on the schematic, yet they are absolutely real. The act of laying out copper quietly adds resistors, inductors, and capacitors you never drew. The layout, in other words, is not a picture of the circuit — it is part of the circuit.
The most important consequence is about return paths. Current always flows in a loop: out along the signal trace and back along its return. The area that loop encloses behaves like an antenna — a small loop is quiet, a large loop both radiates noise and picks it up. So you keep returns short and directly beneath their signals, which is exactly why the next-but-one guide is devoted to the ground plane, an unbroken sheet of copper that gives every signal a short return right underneath it. You also keep noisy returns (a switching regulator, a motor driver, fast digital) separate from quiet ones (sensitive analog), so one circuit's trash does not flow back through another's reference.
For fast or high-frequency signals there is one more layer: a trace stops behaving like a simple wire and acts like a transmission line, and its width together with its distance to the plane below set its controlled impedance — choosing a hose that neither chokes nor wastes the flow. Most slow housekeeping signals never notice, but USB, Ethernet, and RF demand it. The blunt lesson under all of this: a SPICE simulation can prove your schematic works and still be useless, because it sees only the schematic and is blind to your copper. A board can pass simulation and fail on the bench, because the layout you drew added a whole circuit the simulator never knew existed.
Checking it, then handing it off
Before you trust a finished layout, the tool runs a design rule check (DRC). It compares your copper against the rules your fabricator can actually make — is every trace at least the minimum width, is every gap at least the minimum spacing, are there accidental shorts, unrouted nets, or holes crowding too close together? Be clear on what it can and cannot do: DRC confirms the board is manufacturable and matches the netlist. It says nothing about whether the circuit is good — that judgement is still yours. Alongside it sits design-for-manufacture (DFM) thinking: stay inside your fab's comfortable limits rather than its bleeding edge, and yield stays high and cost stays low.
When the DRC is clean, you export the manufacturing files. The classic set is a stack of Gerber files — one image per layer (each copper layer, the solder mask, the silkscreen) — plus a drill file giving the position and diameter of every hole, and a bill of materials (BOM) listing every part to buy and place. The Gerbers and drill file go to the board house that etches the bare board; the BOM and a placement file go to the assembler that solders parts on. The fifth guide in this rung walks that whole handoff in detail.
One last habit to carry up the ladder: real layout is a loop, not a line. You place, route, run DRC, review against the schematic, then re-place to fix what the review found — often several times. When the chip's datasheet offers a known-good reference layout, start from it rather than from a blank board; the manufacturer already paid for the mistakes. And hold onto the through-line as you move into the next guides — trace, via, and pad geometry up close in guide 3, then the ground plane in guide 4: the layout is never merely a drawing of the circuit. It is part of the circuit.