PWM: a switch that is mostly-on or mostly-off
In guide 4 you built a 555 astable and met the duty cycle — the fraction of each period the output spends high. Pulse-width modulation (PWM) takes that idea and makes the duty cycle itself the message. The frequency stays fixed (the carrier), but you slide the width of the high pulse up and down to encode a value. Picture flicking a tap fully open then fully shut, over and over, very fast: hold it open longer each cycle and the bucket fills as though a steady half-flow were running, even though the tap is only ever all-the-way-on or all-the-way-off.
The number a PWM signal really represents is its average value, and the arithmetic is delightfully simple: average voltage = duty times supply. A 30 percent duty cycle on a 5 V supply averages 0.30 times 5 = 1.5 V; a 75 percent duty averages 3.75 V. To turn that average back into a smooth analog level you feed the square wave through a low-pass filter that passes the slow average but blocks the fast carrier — the same humble RC divider you have used all along.
Making PWM: a comparator and a ramp
The cleanest way to generate PWM is a comparator fed two things: a steady triangle or sawtooth ramp, and a reference level you want to encode. The comparator simply asks, every instant, is the ramp below the reference? While it is, the output is high; the moment the ramp climbs past the reference, the output snaps low. Slide the reference up and the ramp spends more of each cycle below it, so the high pulse grows wider — the duty cycle tracks your reference voltage automatically. The ramp's frequency sets the carrier; the reference sets the duty.
PWM = compare a ramp against a reference level
ramp /| /| /| /| (sawtooth, fixed frequency)
/ | / | / | / |
ref ......./..|/..|/..|/..|.... (slide me up or down)
out = HIGH while (ramp < ref), LOW while (ramp > ref)
ref low -> _|‾|____|‾|____|‾|___ duty ~ 20%
ref mid -> _|‾‾‾|__|‾‾‾|__|‾‾‾|_ duty ~ 50%
ref high -> _|‾‾‾‾‾|_|‾‾‾‾‾|_|‾‾‾ duty ~ 90%
average out = duty x supply
duty 0.30, supply 5 V -> 0.30 x 5 = 1.5 VA 555 can do this too — its control pin (pin 5) lets a voltage nudge the charge thresholds, modulating the width — and every modern microcontroller has hardware PWM built from a counter and a compare register doing exactly the ramp-versus-reference job in digital form. Whichever you use, one rule matters: choose the carrier frequency well above the fastest change in your signal, so the averaging filter can smooth the carrier away without smearing the information.
Smoothing PWM into a true analog voltage is a poor man's DAC: pick a low-pass cutoff far below the carrier. With a 1 kHz carrier you might filter at about 100 Hz using R = 16 k and C = 100 nF, since f = 1 / (2 times pi times 16000 times 100 times 10^-9) is roughly 100 Hz. The honest catch is the eternal trade-off: a gentle filter leaves visible ripple at the carrier, while a harder filter cleans the ripple but adds lag, so the output cannot follow a fast-changing duty. There is no free, instant, ripple-free average.
Why PWM is everywhere
PWM's superpower is efficiency. A switch that is fully on drops almost no voltage, and a switch that is fully off carries almost no current — and power wasted is voltage across times current through, so in either state the switch wastes very little. That is exactly the principle behind the switching regulator you met in the power rung, and it is why PWM, not a wasteful linear pass element, controls a motor's speed or a heater's power when you want both control and low loss.
Often the load does the averaging for free. Dim an LED by switching it at a few hundred hertz and your eye, too slow to see the flicker, perceives only the average brightness — duty becomes brightness with no filter at all. A motor's mechanical inertia smooths PWM into smooth torque; a class-D audio amplifier switches the supply at hundreds of kilohertz and lets the loudspeaker and your ears be the low-pass. The trick is the same every time: a fast on/off switch, and something downstream slow enough to average it.
The honest price is noise. Those efficient hard edges are rich in high frequencies that radiate and couple into nearby circuits, so a PWM stage demands good decoupling, tight current loops, and careful layout — exactly the discipline the power and EMC rungs preached. And the carrier never fully disappears: a little ripple always rides on the smoothed output. PWM is the right tool when the load can swallow or filter the carrier; it is the wrong tool when you need a genuinely clean, carrier-free signal at the output.
The VCO: a frequency you steer with a voltage
So far every oscillator you built ran at one frequency set by its parts. A voltage-controlled oscillator (VCO) adds a steering wheel: an input voltage that sets the output frequency. Its key spec is the tuning slope, often called the VCO gain, in hertz per volt. A VCO with a gain of 10 kHz/V centered at 1 MHz moves up to about 1.02 MHz when you raise the control by 2 V and down to about 0.98 MHz when you lower it by 2 V. Feed it a slowly varying voltage and the output frequency dances in step.
There are two everyday ways to build one. At radio frequencies, take an LC oscillator from guide 3 and replace its tuning capacitor with a varactor — a diode whose junction capacitance shrinks as you reverse-bias it harder — so the control voltage tunes the resonant tank directly. At lower frequencies, take a relaxation oscillator (or a 555) and let the control voltage set the charge threshold or the charging current, which changes how long each ramp takes and therefore the period. Both turn a voltage into a frequency; they just lean on resonance versus RC timing.
A taste of the PLL
Now combine the two halves of the last section's dilemma. A VCO is agile but drifts and jitters; a crystal is rock-steady but stuck at one frequency. The phase-locked loop (PLL) marries them with negative feedback: it continuously steers a VCO so its phase locks onto a clean reference. Think of cruise control for frequency, or a dancer who watches a partner and adjusts every step to stay in time — the moment the VCO drifts, the loop corrects it.
Three blocks do the work. A phase detector compares the reference against the VCO's output and puts out an error proportional to how far apart they have drifted. A loop filter (a low-pass) smooths that error into a steady control voltage. That voltage feeds the VCO. Negative feedback drives the phase error toward zero, so the VCO ends up exactly tracking the reference. Slip a divide-by-N counter into the feedback path and the loop must run the VCO N times faster to keep up: output frequency = N times reference. A 1 MHz crystal with N = 100 yields a 100 MHz output as stable as the crystal — that is frequency synthesis, and it is how a CPU makes its gigahertz clock from a cheap few-megahertz crystal.
Stay honest about its limits, because a PLL is a feedback loop and feedback loops can misbehave. Design the loop filter badly and it rings or even oscillates — the very phase margin worries from the op-amp rung apply here too. A PLL only catches a reference within its capture range and only holds it within its (wider) lock range. The loop bandwidth is a genuine trade-off: make it narrow and the output is clean but slow to lock and lets the VCO's own high-offset jitter leak through; make it wide and it locks fast but faithfully copies the reference's jitter. Settling takes real time, and the output is never perfectly jitter-free — only good enough for the job.