DC Errors: Offset, Bias Current, and Drift

The golden rules tell a little white lie

Guide 1 dug into loop gain: how negative feedback drives V+ toward V- and trades the op-amp's raw open-loop gain for a rock-solid closed-loop gain. But those two golden rules quietly assumed two perfect things: that the inputs sit at exactly the same voltage, and that no current flows into them. Real silicon keeps neither promise exactly. The mismatch is tiny — a few microvolts, a few nanoamps — but here is the cruel part: these are DC errors born inside the op-amp, and negative feedback cannot tell them apart from your real signal. The loop faithfully amplifies the error right alongside what you wanted.

Three culprits do the damage. Input offset voltage — the two inputs are not perfectly balanced, so the output is not zero even when they are. Input bias current — the inputs really do draw a thin trickle of current. And input offset current — those two bias currents are not equal to each other. Lurking inside all three is a fourth villain, drift: every one of these numbers wanders with temperature. For AC-coupled audio they barely register, because a series capacitor blocks the DC error outright. For a DC-coupled precision job — an integrator, a sensor bridge, a photodiode amplifier — they are the entire ballgame.

Input offset voltage: a built-in imbalance

Inside every op-amp the two inputs feed a differential pair of supposedly matched transistors. Matched is a goal, never quite a fact — fabrication always leaves them a hair unequal, so the output refuses to be zero when V+ = V-. Input offset voltage (Vos) is simply the small voltage you would have to apply between the inputs to drag the output back to zero. It is a built-in DC error, referred to the input, of typically 1 to 5 mV for a jellybean op-amp and 25 uV or less for a precision part — and its sign is a coin toss from one chip to the next.

Here is the sting: because Vos sits right at the input, the circuit magnifies it by exactly the factor it magnifies any input error — the noise gain, 1 + Rf/Rin. Take a gain-of-10 inverting amplifier with Rin = 10k and Rf = 100k. The signal gain is -Rf/Rin = -10, but the noise gain is 1 + 100/10 = 11 — one more than the signal gain, a detail that trips up almost everyone. With Vos = 2 mV the output carries 11 times 2 mV = 22 mV of pure offset, sitting there even with the input shorted to ground. On a 1 V signal that is already a 2 percent error before you have done anything.

Many op-amps give you trim pins to null Vos to zero, or you can inject a tiny correcting voltage by hand. But be honest about two things. First, Vos is specified as a maximum, with a distribution and an unknowable sign, so you cannot design it to zero on paper — you can only bound the worst case. Second, the null you set this morning has drifted away by this afternoon, which is the whole of a later section. For genuine precision the modern answer is not to trim a sloppy part but to start with a low-offset one.

Bias and offset current: the inputs sip current

The golden rule says no current enters the inputs. Almost true. A BJT-input op-amp's inputs are transistor bases, and a base needs a small current to do its job; a FET-input op-amp's inputs are gates that merely leak a whisper. This input bias current (Ib) runs tens to hundreds of nanoamps for BJT inputs but only picoamps for FET inputs. A current by itself is harmless — the mischief begins when it flows through your feedback resistors and Ohm's law turns it into an unwanted voltage.

Because the error grows with resistance, high-impedance circuits get hurt the most. Picture a transimpedance amplifier turning a photodiode's tiny current into a voltage with Rf = 1 Mohm. A BJT-input part with Ib = 80 nA dumps Ib times Rf = 80 nA x 1 Mohm = 80 mV of error straight onto the output — often larger than the signal itself. Swap in a FET-input op-amp with Ib = 1 pA and the same calculation gives 1 pA x 1 Mohm = 1 uV, utterly negligible. That one comparison is why FET-input op-amps own nearly every high-impedance job.

1. Find the resistance each input sees to ground. For the inverting (-) input of a standard amp it is Rin in parallel with Rf — for the DC calculation both far ends look like ground — so here 10k || 100k = 9.09k. The non-inverting (+) input, wired straight to ground, sees 0 ohm.
2. Spot the imbalance. Bias current flows through 9.09k at the - input but through nothing at the +, so it makes a one-sided error of Ib x 9.09k = 80 nA x 9.09k = 727 uV at the input — which the noise gain then multiplies up at the output.
3. Add a balancing resistor. Insert R+ = Rin || Rf = 9.09k in series with the + input. Now the same Ib makes an equal drop at both inputs; because they appear on opposite inputs, the matched part subtracts out and cancels.
4. What survives is the offset current. The two bias currents are never exactly equal; their difference is the input offset current Ios = |Ib+ - Ib-|, usually a fifth to a tenth of Ib. The leftover error is just Ios x 9.09k = 20 nA x 9.09k = 182 uV — a fourfold improvement for the price of one resistor.

Two honest caveats. The balancing resistor only helps when bias current dominates and the two bias currents track each other; for a FET-input part (picoamp bias) it does more harm than good — it merely adds thermal noise and a node that picks up interference, so tie the + input straight to its reference instead. And beware the integrator: it integrates Vos and bias current forever — the virtual ground never stops feeding that error into the capacitor — so even a perfectly balanced one slowly ramps to a rail, which is why every practical integrator needs a reset switch or a large resistor across the cap.

Drift: nulling a number that won't hold still

Every error so far carries a temperature coefficient. Vos drifts at a few microvolts per °C for an ordinary op-amp — say 5 uV/°C — and under 0.1 uV/°C for a precision one. Make it concrete: trim Vos to zero at 25 °C, then let the board warm to 65 °C inside its enclosure. That 40 °C rise regrows 5 x 40 = 200 uV of offset out of thin air, and in our gain-of-10 stage that is another 11 x 200 uV = 2.2 mV at the output, completely untrimmed. This is the deep reason a one-time null is fragile: you nulled a number that refuses to sit still.

Bias current drifts too, and its direction catches people out. A FET-input op-amp's bias current is gate leakage that roughly doubles every 10 °C, so a part with picoamp bias at room temperature can reach nanoamps when hot — sometimes worse than a BJT part, whose bias current actually eases off a little as it warms. On top of all this sits slow long-term drift from aging, quoted in microvolts per 1000 hours or per month. The lesson: low offset and low bias are room-temperature, day-one numbers; the spec that actually protects you across a product's life and temperature range is the drift.

Picture nulling offset as leveling a table on a slowly tilting floor. Trimming Vos to zero levels the table beautifully — for this one temperature, this one moment. Drift is the floor quietly tilting underneath you. You have two ways to win: buy a table whose legs barely move (a precision, low-drift part), or buy one that re-levels itself constantly. That second idea is real — and it is exactly how the chopper op-amp in the next section works.

Putting it on a budget — and beating it

The professional move is not to fret over any single error but to gather them into a budget. Refer every error to the input, multiply by the noise gain (1 + Rf/Rin), add them up, and compare against what your application can actually tolerate. Here is the whole running example on one card, for our gain-of-10 inverting stage (noise gain 11), with the balancing resistor fitted and the board warm.

  ERROR SOURCE              INPUT-REFERRED          x NOISE GAIN (11)   AT OUTPUT
  ------------------------  ----------------------  -----------------   ---------
  offset voltage Vos        2 mV                    x 11                22 mV
  offset current Ios x R    20 nA x 9.09k = 182 uV  x 11                2.0 mV
  drift  (5uV/C x 40C)      200 uV                  x 11                2.2 mV
  ------------------------  ----------------------  -----------------   ---------
  TOTAL DC error at output  (jellybean op-amp, warm)            ~ 26 mV

  Same circuit, PRECISION op-amp (Vos 25uV, drift 0.1uV/C, Ios 1nA):
    offset voltage 25uV -> 0.28 mV    offset current 9.1uV -> 0.10 mV
    drift 4uV -> 0.044 mV             TOTAL ~ 0.42 mV   (about 60x better)

So you have three real levers. First, pick the right op-amp: a low-Vos, low-drift precision part for DC accuracy; a FET-input part for high-impedance, low-bias jobs; or a chopper / auto-zero op-amp that continuously re-measures and cancels its own offset (Vos in the single-digit microvolts, drift in tens of nanovolts per °C) — exactly the self-re-leveling table, a thermostat that re-checks its own zero thousands of times a second. Second, keep resistances low and balanced so bias current makes little voltage — though not so low that you load the previous stage or waste power, which is a real tradeoff. Third, AC-couple where you can, so a series capacitor blocks the DC error before it is ever amplified; and for the DC-coupled sensor work you cannot AC-couple, the instrumentation amplifier is purpose-built to hold these errors tiny while giving big, accurate gain.