Start from the job, not the circuit
Across this rung you have been collecting a toolbox: the four filter responses, the -3 dB cutoff, the way order steepens the roll-off, and the Q, damping, and op-amp topologies of a real second-order section. Designing a filter is not grabbing one of those at random — it is a design process that runs backwards. You begin with what the circuit must accomplish, you pin that down as numbers, and only then do you choose parts to meet it.
Let us take one honest job and carry it the whole way. We are feeding an analog sensor signal into an ADC that samples at 10 kSa/s. The information we care about lives below 1 kHz; everything above is noise and interference we would happily lose. Before sketching a single resistor, we write the specification: pass the band up to 1 kHz with minimal loss, and attenuate hard enough above the Nyquist frequency that nothing folds back to haunt us.
From spec to order
Two choices fall straight out of the spec. The response is low-pass — keep the low band, shed the high. And the cutoff is where the passband should end, so we set fc = 1 kHz. The hard part is the third choice: how steeply must the curve fall between 1 kHz, where it is still nearly full strength, and the Nyquist edge at 5 kHz (half of 10 kSa/s), where it must already be deep in the stopband?
That steepness is the filter order, and we can solve for it. A Butterworth low-pass attenuates by A = 10 times log10(1 + (f/fc)^(2n)) decibels, where n is the order. Our stopband test sits at f/fc = 5000 / 1000 = 5, and we need at least 48 dB there. Try the orders: a 2nd-order gives 10 log10(1 + 5^4) which is about 28 dB — nowhere near. A 3rd-order gives 10 log10(1 + 5^6), about 42 dB — close but still short. A 4th-order gives 10 log10(1 + 5^8), about 56 dB — clearing 48 dB with margin. So we round up to order 4.
THE JOB -> THE FILTER (anti-alias ahead of a 10 kSa/s ADC)
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spec pass <= 1 kHz ; >= 48 dB down by 5 kHz (Nyquist)
response low-pass
cutoff fc 1 kHz
order attenuation at f/fc = 5 :
2nd -> ~28 dB (short)
3rd -> ~42 dB (short)
4th -> ~56 dB (clears 48 dB) <== pick this
approximation Butterworth (flat passband; phase not critical)
topology two cascaded 2nd-order Sallen-Key sections
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A 4th-order Butterworth = two stages, SAME fc, DIFFERENT Q :
stage 1 fc = 1 kHz Q = 0.54 (well damped, no peak)
stage 2 fc = 1 kHz Q = 1.31 (peaks ~3 dB just below fc)
the gentle stage and the peaky stage multiply into one flat curveNotice how forgiving this job was: a whole factor of five (1 kHz up to 5 kHz) for the response to fall in. That is why order 4 sufficed. Had the spec instead asked us to pass 4 kHz yet reject at 5 kHz — a mere 1.25 times — the required order would explode into the teens, an unbuildable monster. This is the real reason fast systems oversample: sampling far above twice the signal band opens a wide, cheap transition gap and lets a gentle filter do the work. When the analog filter looks impossible, raise the sample rate, do not raise the order.
Choosing the response shape and the topology
Order in hand, which flavour of 4th-order? Guide 4 framed the trade. For an anti-alias filter we most want a flat passband so we do not colour the signal, and we do not much care about phase, so the Butterworth (maximally flat) is the natural pick. Had we needed an even steeper cliff from the same order, we could have switched to a Chebyshev, buying steepness with ripple inside the passband. And if this filter were smoothing a pulse or step whose shape mattered, we would reach for a Bessel to keep its phase linear and its step clean — but here, Butterworth it is.
Now the circuit. You do not build a 4th-order filter as one lump; you cascade two second-order sections — exactly the Sallen-Key block from guide 3 — one feeding the next. Both sections are tuned to the same fc = 1 kHz, but, and this is the subtle part, each gets a different Q read straight from a Butterworth design table: 0.54 for one section, 1.31 for the other. Their job is teamwork, not identical copies.
Why two unequal Qs? Look at what each does at the corner. The Q = 0.54 section is heavily damped and sags a little early; the Q = 1.31 section peaks about 3 dB just below fc. Multiply the two responses together and the peak fills the sag, leaving one beautifully flat curve that crosses -3 dB at exactly 1 kHz and then plunges at 80 dB per decade. (A Sallen-Key sets each Q through its resistor and capacitor ratios; if you preferred, the inverting multiple-feedback topology reaches the same response and often stays quieter at higher Q.)
Real parts, and wiring it into the chain
Time for real numbers. In each Sallen-Key section the corner is fc = 1 / (2 times pi times R times C), the same relation as the humble RC. Pick a sane capacitor first — say C = 100 nF — and solve for the resistor: R = 1 / (2 times pi times 1000 times 100 times 10^-9) which is about 1592 ohm, so reach for a standard 1.6 k. Each stage then realises its particular Q through the ratio of its two capacitors (or two resistors), the mechanism guide 3 walked through: the absolute RC product sets where the corner sits, the ratio sets how peaky it is.
Two cautions turn a paper design into a working one. First, real parts come in tolerance grades: 5 percent resistors and capacitors let the corner — which goes as 1/(RC) — and the Q wander, and the errors stack. For a filter whose edge must land where you promised, select 1 percent resistors and good film capacitors, and leave yourself some margin. Second, you will round that 1592 ohm to a stock value, so recompute the actual fc and Q after rounding rather than assuming the catalogue value was exact.
The op-amp is the last decision, and the loading worry from earlier guides mostly vanishes here: a Sallen-Key's output is driven by the op-amp, so each stage presents a low output impedance to the next stage and to the ADC. You do still need enough op-amp speed — a safe rule of thumb is a gain-bandwidth product at least fifty to a hundred times Q times fc, plus a slew rate that handles full output swing at the top frequency. At fc = 1 kHz almost any modern op-amp laughs at that, but lift the same design to a 100 kHz or 1 MHz filter and the op-amp's GBW and slew rate become the binding constraint that decides which part you can buy.
- Write the numeric spec from the job: the band to pass, the band to reject and by how much, the supply you will run on, and the signal level you must preserve.
- Choose the response (low / high / band / notch) and set the cutoff where the passband must end.
- Solve for the minimum order from the required stopband attenuation, then round up — there is always margin in rounding up, never in rounding down.
- Choose the approximation from what matters most: Butterworth for a flat passband, Chebyshev for the steepest edge at the cost of ripple, Bessel for clean phase and pulse shape.
- Map the order onto cascaded second-order sections; read each section's Q from a design table; pick a topology (Sallen-Key, or multiple-feedback for higher Q).
- Choose C, solve R, round to stock values, then recompute the real fc and Q; use tight-tolerance parts wherever the edge must be precise.
- Pick an op-amp with enough GBW and slew rate, confirm loading and supply, then simulate, build, and measure — and trust the measurement above all.
Verify — and the limits you cannot design away
Before you trust the board, simulate it. An AC analysis sweeps frequency and draws the magnitude and phase, letting you confirm the passband is flat, the -3 dB corner truly sits at 1 kHz, and the response is at least 48 dB down at 5 kHz. A transient analysis feeds a step or a square wave and shows the overshoot and ringing — the visible price of that Q = 1.31 section, and exactly where you would compare a Butterworth against a calmer Bessel if pulse shape mattered.
But a simulation is only as honest as its models, and it is blind to your physical build. It cannot see the stray capacitance of a breadboard, whose few picofarads quietly shift a corner and can wreck a higher-frequency filter outright; it cannot see a sloppy PCB layout where a shared ground return or a long trace becomes an accidental circuit element. The simulator draws the schematic you meant; the bench measures the circuit you actually built. When the two disagree, the bench is right.