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The CMOS Inverter: Bridge to Digital

Two complementary MOSFETs, one on top of the other, make the single most important circuit in modern electronics. Watch the amplifier you built in guide 3 turn into a digital logic gate that burns almost no power when idle — and meet the honest catch hiding in every transition.

From amplifier to switch — and why digital wants both

In guide 3 you built a common-source amplifier — a MOSFET in its high-gain region, turning a small wiggle at the gate into a big swing at the drain. In guides 1 and 2 you used the same device as a switch: drive the gate hard and it is either fully on (a low on-resistance) or fully off. A digital gate lives at the meeting point of those two ideas. Almost all the time it sits parked as a switch, but in the instant it flips it must pass through the amplifier region. The CMOS inverter is the circuit that marries the two — and it is the bridge from everything analog you have learned to the digital world.

Here is the snag with the simplest digital switch. An NMOS transistor can pull its output down to ground when you turn it on, but it cannot pull the output back up — so you need something to do the lifting when it is off. The classic answer is a plain pull-up resistor to the supply. It works, but it is wasteful: whenever the output is low, the resistor pours current straight from the supply to ground, and when the output rises it does so weakly and slowly through that resistor. CMOS replaces that lazy resistor with a second, complementary transistor that pulls up actively — and that one swap changes everything.

The CMOS inverter: two complementary switches

CMOS stands for Complementary MOS, and the inverter is the simplest CMOS circuit there is. Stack a P-channel MOSFET on top (its source to the positive supply) and an N-channel MOSFET on the bottom (its source to ground). Tie both gates together — that is the input. Tie both drains together — that is the output. Both are ordinary enhancement-mode devices, off until their gate passes the threshold voltage. That is the entire part: two transistors, complementary types, sharing a gate and a drain.

                 +Vdd
                  |
              +---+---+
   IN o------o|  PMOS |   (ON when IN is LOW)
              +---+---+
                  |
                  o------o OUT
                  |
              +---+---+
   IN o------o|  NMOS |   (ON when IN is HIGH)
              +---+---+
                  |
                 GND

  IN = LOW   -> PMOS on,  NMOS off  -> OUT = HIGH (pulled to Vdd)
  IN = HIGH  -> PMOS off, NMOS on   -> OUT = LOW  (pulled to GND)
  stable state: exactly ONE device on -> no Vdd-to-GND path -> ~0 static current
The CMOS inverter: a PMOS pull-up and an NMOS pull-down sharing one gate and one drain.

Now walk the two stable states. Drive the input low: the NMOS sees no gate drive and stays off, while the PMOS — whose gate is now well below its source — turns hard on and ties the output up to the supply. Drive the input high: the PMOS shuts off and the NMOS turns on, tying the output down to ground. In both resting states exactly one transistor is on and the other is a near-perfect open switch, so there is no continuous path from supply to ground. The static current is essentially zero — just tiny leakage. That single fact is why CMOS conquered electronics: a chip with a billion idle gates sips almost nothing.

The transfer curve, logic levels, and noise margin

Sweep the input slowly from 0 up to the supply and plot the output: that is the voltage transfer characteristic. It is flat and high at first, then drops almost vertically through the middle, then sits flat and low. That steep middle stretch is the surprise — it is the inverter behaving as a high-gain common-source amplifier. In that narrow band both transistors are partly on and in saturation, each acting as the other's active load, and the voltage gain is tens to hundreds. The analog amplifier from guide 3 is literally hiding inside the digital gate; the gate just spends as little time there as possible.

That steepness is what makes digital logic robust. Because the output snaps to one rail or the other, a sloppy input that is merely near a rail still produces a clean output right at the rail — the gate restores the signal every time it passes through. We name the safe bands logic levels: any input below a low threshold reads as a 0, any input above a high threshold reads as a 1, and the gap between the worst guaranteed output and the input level still read correctly is the noise margin — the cushion that lets a wire pick up a bit of noise without flipping a bit. On a 5 V CMOS gate the output highs sit near 5 V and lows near 0 V, the switching point is around 2.5 V, and the noise margins are roughly 2 V on each side — about 40 percent of the supply, far more generous than older logic families.

Where the power actually goes

If a resting CMOS gate burns almost nothing, why does a busy processor get hot? The answer is that almost all the power is spent in the act of switching, not in the resting states. Every time the output flips, the capacitance hanging on it — mostly the gate capacitance of the next gates it feeds, the very gate charge you met in guide 4 — has to be charged up through the PMOS on a rising edge and dumped through the NMOS on a falling edge. Each full charge-then-discharge cycle dissipates an energy of C times V^2, no matter how big the transistors are.

Put numbers on it. A node carrying a load of C = 10 pF = 10^-11 F, swinging V = 3.3 V, toggling at f = 100 MHz, dissipates P = C times V^2 times f = 10^-11 times 3.3^2 times 10^8 ≈ 10.9 mW. Multiply that by millions of switching nodes and you see why CPUs need fans. Two honest footnotes: real chips multiply this by an activity factor (most nodes are not switching on every single clock), so the true average is P = (activity) times C times V^2 times f; and notice V is squared — halving the supply quarters the dynamic power, which is exactly why every generation of chips chases a lower voltage.

There is a second, sneakier loss. During the brief instant the input is mid-way and both transistors are partly on, a short-circuit current punches straight from supply to ground — a spike of crowbar current that adds to the switching losses. Slow input edges widen that overlap window and waste more, which is another reason you want sharp edges. Those current spikes also yank on the supply rail, so you place a decoupling capacitor right next to the chip: a little local water tank beside the thirsty gate, so the long supply pipe never sags during the gulp.

Honest notes: the gate is a capacitor, and it's fragile

Hold on to the real picture of that input. The great charm of the MOSFET versus the BJT is that the gate draws essentially no steady current — but the gate IS a capacitor, and a capacitor draws a current spike every time its voltage changes. At DC, switching it costs nothing; at a gigahertz, moving that gate charge back and forth a billion times a second is the entire power budget. The famous 'no gate current' rule is a DC truth, not an AC one — there is no free lunch, only a bill that arrives faster the faster you switch.

Step back and see how far you have come. You started this rung with a single voltage-controlled switch, contrasted it with the current-hungry BJT, built MOSFET amplifiers and source-followers, learned to drive a power device's gate, and now you hold the building block of every processor, memory, and logic chip on Earth: billions of these complementary pairs, each one a clean inverter. The CMOS inverter is the bridge — on one bank, all the analog craft of the field-effect transistor you have mastered; on the other, the digital logic, memory, and CPUs of the rungs to come. The deepest honest takeaway: digital is not a different physics, it is just analog that we let settle all the way to the rails.