The one question every ADC asks
Across this rung you have crossed the analog/digital divide piece by piece: guide 1 showed how sampling freezes a continuous signal at clock ticks, guide 2 showed why aliasing forces an anti-alias filter ahead of those ticks, guide 3 turned amplitude into numbered codes and gave us resolution and ENOB, and guide 4 ran a DAC forwards to turn codes back into volts. An ADC runs that last step in reverse, and underneath all its cleverness it is asking one blunt question: how many of the smallest steps — how many LSBs — of the reference does this input voltage equal? The answer is a code from 0 up to 2^n minus 1.
Two parts make that possible. The reference is the silent ruler: every ADC compares the input only against fractions of Vref, so Vref sets full scale, and any noise or drift in it lands straight in your answer as error. The other part is the comparator — the electronic eye that looks at two voltages and says only 'the left one is higher' or 'the left one is lower'. Strip away the marketing and every converter is just a clever way of pointing one or more comparators at the input and the reference and reading off where the input sits. Where the families differ is purely in how they conduct that search.
Hold one picture in your head for the whole guide: a staircase of 2^n codes, and the ADC trying to find which step the input lands on. You can interrogate every step at once, you can play a binary-search guessing game one bit at a time, or you can take a torrent of crude looks and average them. Those three strategies are flash, SAR, and sigma-delta — and the choice between them is the same three-way tradeoff that haunts all of electronics: speed against resolution against cost and power. You cannot maximise all three at once.
Flash: ask every question at once
The flash ADC is the brute-force champion: it hires one comparator for every threshold and lets them all vote at the same instant. A resistor ladder — a long chain of equal resistors across Vref, the voltage divider from the very first rung repeated many times — taps out one reference level per code. Each of the 2^n minus 1 comparators holds the input against its own tap, so the outputs read like a thermometer: all the comparators below the input read high, all above read low, and the boundary marks the answer. A priority encoder reads off where the thermometer turns over and spits out the binary code, all in a single clock tick.
That parallelism is breathtakingly fast — flash converters reach billions of samples per second and live in the front ends of fast oscilloscopes and radio receivers — but the cost is merciless. The comparator count is 2^n minus 1, so it doubles with every added bit: an 8-bit flash needs 2^8 minus 1 = 255 comparators, a 10-bit needs 1023, a 12-bit over four thousand. Each comparator also adds input capacitance and burns power, so the whole array becomes a heavy, hot load that your signal source must drive. Flash trades silicon and watts for raw speed, with no patience to spare.
Be honest about where the ceiling really is. Beyond about 8 bits a plain flash is rarely worth it: the comparator count explodes, the input capacitance becomes hard to drive, and matching all those ladder taps and comparator offsets to better than one LSB grows brutal. Designers stretch the idea with pipelined and folding architectures that reuse a small flash stage many times — a sensible middle ground for fast, medium-resolution work — but the pure flash itself stays a specialist: choose it when you need extreme speed and can live with modest resolution.
SAR: a binary search with a DAC inside
The successive-approximation (SAR) ADC plays the guess-the-number game. Think of finding a hidden number between 0 and 15 by asking only 'higher or lower?': you guess 8 first (the middle), then 4 or 12, and so on, pinning one bit per question. Inside, a SAR converter wires up exactly the parts to do this: a sample-and-hold to freeze the input, a single comparator, a small DAC (the binary-weighted or R-2R ladder of guide 4, or in modern chips a charge-redistribution capacitor array), and the SAR logic. Each clock cycle it sets one trial bit, the DAC turns the trial code into a trial voltage, and the comparator says keep this bit or clear it. An n-bit conversion takes n cycles — one careful question per bit.
- Set the stage with real numbers: a 4-bit SAR, reference Vref = 5 V, so one LSB = 5 V / 2^4 = 5 / 16 = 0.3125 V. The held input is Vin = 3.0 V. We will build the code from the most significant bit down.
- Bit 3 (weight 8): try code 1000 -> DAC = 8 times 0.3125 = 2.5 V. Is 3.0 V higher? Yes, so keep the bit. Code so far = 1000.
- Bit 2 (weight 4): try code 1100 -> DAC = 12 times 0.3125 = 3.75 V. Is 3.0 V higher? No, so clear the bit. Code back to 1000.
- Bit 1 (weight 2): try code 1010 -> DAC = 10 times 0.3125 = 3.125 V. Is 3.0 V higher? No, clear it. Code stays 1000.
- Bit 0 (weight 1): try code 1001 -> DAC = 9 times 0.3125 = 2.8125 V. Is 3.0 V higher? Yes, keep it. Final code = 1001 = 9, which reads back as 2.8125 V — the staircase step just below 3.0 V, leaving a quantization error of 0.1875 V, well under one LSB. Four clocks, four bits, done.
This binary search is why SAR is the workhorse of the converter world. It needs only one comparator and one DAC no matter the resolution, so it stays small, low-power, and cheap while reaching 8 to 18 bits at hundreds of kilosamples to several megasamples per second. It is the very ADC built into most microcontrollers. Two honest cautions, though: the sample-and-hold is mandatory, because the input must hold perfectly still across all n comparisons, and the converter is only as good as its internal DAC — any nonlinearity in those binary-weighted elements shows up directly as nonlinearity in the result.
Sigma-delta: trade speed for resolution by oversampling
The sigma-delta ADC refuses the careful single look and instead takes a torrent of crude ones. A simple loop — an integrator, a comparator acting as a 1-bit ADC, and a 1-bit DAC fed back to subtract — runs far faster than the signal needs, pouring out a dense stream of ones and zeros whose average density tracks the input. Feed in half-scale and the bitstream is about half ones; feed in near full scale and it is mostly ones. A digital filter then counts and smooths that stream into a high-resolution number. The genius is that a 1-bit converter cannot be nonlinear (two points always lie on a straight line), so it sidesteps the matching problems that limit flash and SAR.
Two ideas from guide 3 do the heavy lifting. The first is oversampling: the total quantization noise is fixed, so sampling far above Nyquist spreads it across a much wider band, and only the slice inside your signal band counts. Plain oversampling buys roughly one extra bit for every 4x in rate (about 6 dB of SNR). The second, and the real magic, is noise shaping: the feedback loop does not just spread the quantization noise evenly — it actively pushes it up to high frequencies, out of the band you care about, where the digital filter then deletes it. Together they let a humble 1-bit core reach 16 to 24 effective bits. A final decimation stage throws away the excess samples and hands you the slow, clean, high-resolution output.
The honest tradeoffs are the mirror image of flash. Sigma-delta is slow: it needs many internal cycles per output sample, and the digital filter adds latency, so it is wrong for snapping fast one-shot events or rapidly hopping between channels. But for audio and for slow, precise DC measurement from sensors it is unbeatable. It carries a quiet bonus too: because it samples so far above the band of interest, the analog anti-alias filter in front of it can be gentle and cheap rather than a steep monster (recall the wide, forgiving transition gap from guide 2). It still obeys Nyquist at its final output rate, though — its decimated result can still suffer aliasing, so the modest filter is relaxed, never absent.
Dual-slope, and an honest comparison
A fourth family rounds out the picture: the dual-slope (integrating) converter, the balance-scale of ADCs. It charges an integrator from the unknown input for a fixed time T1, then switches to a known reference of the opposite polarity and times how long, T2, it takes to ramp back to zero. The ratio falls out beautifully as Vin / Vref = T2 / T1 — and notice the integrator's capacitor and resistor cancel out of that ratio entirely, so their drift and tolerance simply do not matter. That immunity is why dual-slope is wonderfully stable and accurate. Pick T1 as a whole number of mains periods (100 ms is exactly 5 cycles of 50 Hz and 6 of 60 Hz) and the mains hum integrates to zero, rejecting the very interference that plagues everything else. It is slow — a handful to a few hundred conversions per second — which is exactly why it lives inside the bench multimeter.
FAMILY RESOLUTION SPEED HARDWARE COST BEST FOR ------------------------------------------------------------------------------ Flash 6-8 bits fastest ~2^n comparators scopes, RF front-ends SAR 8-18 bits fast 1 comparator + DAC MCUs, general DAQ Sigma-delta 16-24 bits slow 1-bit loop + filter audio, precision DC Dual-slope 12-22 bits slowest integrator + timer bench multimeters ------------------------------------------------------------------------------ one conversion: flash = 1 clock SAR = n clocks S-D / dual-slope = many always the same triangle: SPEED <-> RESOLUTION <-> COST / POWER
Whichever family you pick, read the same handful of specs honestly. Conversion time is how long one answer takes; throughput is how many answers per second you actually get, including the sample-and-hold's acquisition time and any pipeline delay — they are not the same number. INL measures how far the whole transfer curve bows away from a straight line (in LSBs), while DNL measures how far each individual step strays from one LSB wide; a DNL worse than minus one LSB means a code is missing entirely — a step the converter can never output. And tying it all back to guide 3, the ENOB is the number that tells you how many of those advertised bits are real once noise and distortion are counted.
Wiring an ADC to a microcontroller
Most of the time you do not build any of this — you use the SAR ADC already inside your microcontroller (typically 10 to 12 bits), or you bolt on an external converter over an SPI or I2C bus when you need more resolution or speed. Either way, the first decision is the reference, because it sets full scale and therefore the meaning of every code. A noisy or drifting reference quietly steals bits; a clean, stable one earns its place. A neat trick when you are measuring a ratio (a sensor divider, say) is to power both the sensor and the reference from the same supply, so a supply wobble cancels in the ratio instead of becoming an error.
The classic real-world bug is the acquisition time. The sample-and-hold's hold capacitor must charge through your source's resistance before the converter reads it, and that is an RC settling exactly like the early rungs taught. If your signal comes from a high source impedance — a big divider, a sensor through a long lead — the cap cannot fill in the brief sample window and every reading sags low. The cure is to put a buffer (an op-amp follower, with its near-zero output impedance) right before the ADC, and of course the anti-alias filter still goes first, ahead of any sampling. Then mind the layout: a real ADC needs a solid decoupling capacitor right at its supply and reference pins, because on a real board the layout itself is a circuit element, and reference noise turns straight into conversion error.