From a number back to a voltage
The first three guides in this rung ran one direction: a smooth analog signal was sampled in time and then chopped vertically into a finite ladder of codes by quantization. A digital-to-analog converter runs that film backwards. Hand it an n-bit number and it hands back a voltage — one of 2^n possible levels, each exactly one LSB tall, with the whole span pinned by a reference. It is the exit door from the digital world back into the analog one.
Concretely: take an 8-bit DAC with a 2.56 V reference. The step size is LSB = 2.56 / 256 = 10 mV, so the output is simply the code times the LSB. Code 100 gives 100 times 10 mV = 1.000 V; the full code 255 gives 2.55 V. Notice full scale lands one LSB below the reference (it is 2^n - 1 steps, not 2^n) — a tidy reminder that an n-bit DAC has 2^n levels but only 2^n - 1 gaps between them. This resolution is exactly the mirror of the quantization grid from guide 3.
The binary-weighted DAC: just a summing amplifier
The most intuitive DAC is something you already built in the op-amp rung: a summing amplifier. Picture an inverting op-amp whose virtual ground collects current from several input resistors. Now make those resistors binary-weighted — R, 2R, 4R, 8R, and so on — and let each bit be a switch that ties its resistor either to the reference (a 1) or to ground (a 0). The most-significant bit gets the smallest resistor and therefore pours in the largest current; each lower bit, through a doubled resistor, contributes exactly half as much. The op-amp adds it all up and converts the total current into an output voltage. That is the whole binary-weighted DAC.
The arithmetic falls out cleanly. For a 4-bit version with feedback resistor Rf, the output is Vout = -(Rf times Vref / R) times (b3 + b2/2 + b1/4 + b0/8), where each b is 0 or 1. Every bit weighs in at exactly half the bit above it — the very definition of binary place value — so the codes march in even LSB steps from zero to full scale. It is direct, it is fast (flip a switch and the current is simply there), and for 4 to 6 bits it is perfectly serviceable.
But the binary weighting that makes it elegant also kills it past a few bits: the resistor spread. An 8-bit DAC needs values from R up to 128R — a 128-to-1 range; a 12-bit DAC needs 2048-to-1. To keep even the LSB honest to half a step, the largest resistor must match the smallest to better than about 0.4 percent — and matching, say, a 1.28 MΩ part to a 10 kΩ part that tightly, and over temperature, is essentially unmanufacturable. The tolerance you can buy on a single resistor is fine; the tolerance you need across a thousandfold spread is not. That single problem is why a smarter ladder had to be invented.
The R-2R ladder: precision from just two values
The fix is beautiful: build the whole converter from only two resistor values, R and 2R. The R-2R ladder is a self-similar network in which the current splits exactly in half at every node, so successive bits get currents of I/2, I/4, I/8, ... — perfect binary weights — using nothing but copies of the same two resistors. And the only thing that must be accurate is the 2-to-1 ratio. If you build each 2R as two R resistors in series, every resistor on the chip is identical, drifts identically, and a precise ratio is far, far easier to manufacture than a precise 2000-to-1 spread.
R-2R LADDER DAC (4-bit, current-steering; MSB = b3 at the Vref end)
Vref
|
A---[R]---B---[R]---C---[R]---D---[2R]---GND (R rail on top, 2R end-stop)
| | | |
[2R] [2R] [2R] [2R]
| | | |
sw3 sw2 sw1 sw0 each switch: 0 -> GND , 1 -> IOUT
\_________\_________\_________/
IOUT --> op-amp summing node, held at 0 V (virtual ground)
Both rails sit at 0 V, so the ladder current is FIXED by Vref; the
code only steers each leg toward GND or toward the summing node.
Looking right from any node you see 2R, and its own leg is 2R, so the
current halves at every node:
b3 = I/2 , b2 = I/4 , b1 = I/8 , b0 = I/16 (binary weights)Why does it halve so perfectly? Use Thévenin's eye. Start at the far node: the 2R termination to ground and that node's own 2R leg both go to 0 V, so looking right from the next node you see R series plus (2R parallel 2R = R) = 2R. Move one node left and the same thing repeats — by self-similarity every node sees exactly 2R looking onward and 2R down its own leg. Two equal resistances split the incoming current evenly, so each leg carries half of what flowed into its node: I/2, then I/4, then I/8, the binary cascade falling out of pure geometry.
There is an extra prize hiding in the switches. Each leg's switch routes its current to either ground or the op-amp's virtual ground summing node — and both of those points sit at 0 V. So flipping a bit never changes the amount of current in the ladder; it only changes its destination. The total ladder current stays rock-steady regardless of the code, which makes the converter fast and dramatically lowers the switching glitches you would otherwise get. That combination — only two resistor values and a code-independent current — is why nearly every precision resistor-network DAC on the market is an R-2R inside.
The reference, the switches, and the specs that bite
A DAC's full scale is set entirely by its voltage reference — the output is ratiometric, equal to (code / 2^n) times Vref. That is a double-edged fact: nothing in the DAC is more accurate than its reference, and any noise or temperature drift on Vref scales straight onto every single code. A 12-bit converter resolving 4096 levels deserves a stable, low-noise bandgap reference, not a casual tap off the supply rail — feed it the noisy 5 V logic supply as a reference and you have thrown away your lower bits before the ladder even gets a turn.
The switches are not ideal either. Real bit switches are MOSFET analog switches with their own on-resistance, which adds in series with each 2R leg and nudges its weight off. Good DACs trim this out or scale the switch sizes so larger-current legs get fatter, lower-resistance switches — and the R-2R's constant-current trick helps again, because every switch always works across the same 0 V whatever the code. This is exactly the kind of detail simulation can miss: a SPICE model of ideal switches will show a flawless transfer curve the real silicon never quite delivers.
Two specs decide whether a DAC is honest. Differential nonlinearity (DNL) measures how far each single step strays from one ideal LSB; integral nonlinearity (INL) measures the worst bend of the whole curve away from a straight line. DNL has teeth: if any step's DNL is worse than -1 LSB, the output actually goes down when the code goes up — the DAC is non-monotonic, which can break a feedback loop that trusted it to move the right way. The danger zone is the major-carry transition (0111... to 1000...), where the biggest leg switches in while a crowd of smaller ones switch out; mismatched timing there throws a glitch the settling time and a deglitcher must absorb.
From staircase to smooth: reconstruction and using it
A DAC does not draw smooth curves — it draws a staircase. Each code is held flat until the next sample arrives (a zero-order hold), and that blocky waveform is full of high-frequency images sitting above your real signal, the exact mirror of the aliasing problem from guides 1 and 2. So a DAC's output must be followed by a low-pass reconstruction filter that smooths the steps and erases those images, just as an anti-alias filter guards the input of an ADC. (The hold itself also gently tilts the high end down — the sinc droop — which a careful design pre-compensates.) As always, you must update faster than twice the highest frequency you want to reproduce, or Nyquist takes its revenge no filter can repair.
Sometimes you do not even need a dedicated DAC chip. A microcontroller pin toggled with PWM and then low-pass filtered is a poor man's 1-bit DAC: the duty cycle sets the average voltage, and the same reconstruction filter smooths the pulse train into a level. It is genuinely useful for LED brightness or a slow control voltage, but be honest about the trade — resolution fights against speed (more bits means a slower update rate or a higher clock), and the ripple left behind is the price of cheating. A real R-2R or sigma-delta DAC earns its keep the moment you need clean audio or many fast, accurate bits.
- Pick resolution and reference so one LSB is finer than the smallest step you care about: needed LSB = full scale / 2^n, so a 1 mV LSB over a 4.096 V span wants 12 bits with a 4.096 V reference.
- Wire the digital bus (SPI or I2C for a serial DAC), and decouple both the supply and the reference pins with a capacitor right at the chip — the reference especially must be quiet.
- Write the code word; the analog output appears as code / 2^n times Vref. Sanity-check with a multimeter at a few codes (zero, mid, full) before trusting the curve.
- Add the reconstruction low-pass with its corner near your signal band (well below half the update rate) to smooth the staircase, and buffer it with an op-amp follower if the load draws real current.
Step back and the picture is whole. A DAC turns a number into a voltage; the binary-weighted form makes that obvious as a summing amplifier but drowns in resistor spread, and the R-2R ladder rescues it with two values and a self-halving current. A clean reference sets the scale, the switches and INL/DNL set the honesty, and a reconstruction filter turns the staircase back into a signal. And because this exact block is the heart of a SAR converter, you have already built half of the ADC — which is precisely where guide 5 picks up.