Designing a Chip: the IC Design Flow

Start with a spec

Before anyone draws a single wire, the design starts as a wish list. What must this chip actually do? Maybe it decodes video, or runs a phone's brain, or measures a heartbeat. That wish list, written down precisely, is called the spec — short for specification. Think of it as the architect's brief before a building exists: how many rooms, how tall, how much it can cost.

A real spec is mostly about three numbers people argue over endlessly: how fast it runs, how much power it burns, and how much chip area (and therefore money) it takes. These three pull against each other like a three-way tug-of-war — make it faster and it usually gets hotter and bigger. The whole craft of chip design is finding a sweet spot between them.

From the spec, engineers sketch the architecture — the big blocks and how they connect, like a floor plan that says 'kitchen here, bedrooms there.' Then they zoom in to the microarchitecture: exactly how each block does its job, step by step. All of this is decided on paper and in documents long before any layout exists. Get the plan wrong here and no amount of clever wiring later will save it.

Describe behavior in RTL

Once the plan is settled, designers don't draw transistors — they write code. Using a hardware description language like Verilog or VHDL, they describe what the chip should do at the register-transfer level, or RTL for short. The name sounds heavy, but the idea is friendly: you describe how data moves from one little storage box (a register) to the next on every tick of the clock, and what gets computed along the way.

Here's the part that trips up newcomers: this looks like software, but it is not a recipe of steps run one after another. Every line you write becomes real hardware that exists all at once, running in parallel. Writing RTL is less like writing a to-do list and more like describing a whole orchestra that all plays together on each beat of the conductor's baton — the clock.

// an 8-bit register: on each rising clock edge,
// load new data, unless reset is held
always @(posedge clk) begin
  if (reset)
    count <= 8'd0;       // clear to zero
  else
    count <= count + 1;  // otherwise count up
end

A tiny counter in Verilog. 'posedge clk' means 'on the clock's rising tick'; each tick, count goes up by one — or resets to zero.

Read that block above slowly and you can almost hear it: every time the clock ticks upward, the counter either clears to zero or nudges up by one. A whole chip is thousands of small descriptions like this, stitched together. Once the RTL is written, the human part is largely done — from here on, software takes the wheel.

Synthesis → logic gates

Your RTL says what should happen, but it doesn't yet say which real parts will do it. A tool called a synthesizer does that translation. Feed it your code, and it compiles those behavioral descriptions down into a netlist — a precise list of actual logic gates (AND, OR, NOT, and friends) and exactly how they wire together to produce the behavior you described.

It helps to compare it to ordinary programming: writing RTL is like writing in a high-level language, and synthesis is the compiler that turns it into something the hardware world can actually build. Except instead of producing machine instructions, it produces a wiring diagram of gates — and it picks each gate from a pre-made catalog of building blocks, which we'll meet next.

Standard cells, place & route

Those gates in the netlist aren't designed from scratch each time. The foundry hands you a library of ready-made little building blocks called standard cells — a pre-drawn AND gate, a pre-drawn flip-flop, and so on, each one a tidy tile of the same height, like LEGO bricks made to snap into neat rows. Your netlist is now a giant bill of materials: thousands or millions of these bricks.

Now comes physical design, and the tool's job is gorgeously concrete. First it floorplans the die — deciding which big regions go where on the silicon rectangle. Then it places every cell into a real spot. Then it routes the metal wires that connect them all, stacking connections across many layers like roads, bridges, and tunnels in a crowded city. This whole packing-and-wiring job is called place and route.

And it can't just cram things anywhere. The tool is constantly checking it stays inside the area budget (the chip can't grow too big) and the power budget (it can't draw too much current), all while keeping the wires short enough that signals arrive on time. It's a packing puzzle the size of a city, solved in hours.

Verification & timing

Running through all of that, and especially before committing to manufacture, the design has to be proven correct — because you can't patch a chip after it ships. Verification is the safety net, and it comes in a few flavors. Simulation feeds the design pretend inputs and checks the outputs, like a flight simulator before a real flight. Formal checks go further, using math to prove a property holds for every possible input, not just the ones you happened to try.

The trickiest promise to keep is timing. Remember the clock that beats out the rhythm? Every signal that leaves a register has to travel through its gates and arrive at the next register before the next clock tick. If even one path is too slow, that beat catches the signal mid-journey and the chip computes garbage. Getting every single path to settle in time is called timing closure — and on a big chip there can be millions of paths to check.

Tape-out

When verification passes and every path closes timing, the design reaches its big moment: sign-off. Teams run a last battery of checks, everyone who must approve does, and then the finished design is sent to the factory — the foundry — as a set of masks, the stencils the factory uses to print the chip onto silicon. This release is called tape-out.

The funny old name comes from the days when finished designs were literally written onto a reel of magnetic tape and carried out the door to the fab. The tape is long gone, but the weight of the moment isn't: once you tape out, you can't take it back. The masks get made, the wafers get printed, and weeks later the first real chips come home to be tested.

What EDA tools do

Step back and look at the whole journey, and one fact jumps out: a person did the thinking, but software did the building. The synthesizer, the placer, the router, the timing checker, the verification engines — they're all part of a category called EDA, short for Electronic Design Automation. Every stage you just read about runs on EDA software.

And there's a simple reason it has to be this way. A modern chip can hold tens of billions of transistors. If you placed one per second, by hand, without ever sleeping, you'd still be at it for centuries. No human, and no team of humans, designs a chip of that size by hand — the scale is simply beyond us. EDA is what makes the impossible routine.

Spec: pin down what the chip must do, and its speed, power, and area budgets.
RTL: describe the behavior in Verilog or VHDL, register by register, clock tick by clock tick.
Synthesis: compile that RTL into a netlist of logic gates and standard cells.
Place & route: floorplan the die, place every cell, route the metal wires, within budget.
Verify & close timing: simulate, prove, and make sure every path beats the clock.
Tape-out: sign off and send the masks to the foundry — the point of no return.

So the next time you hold a phone, remember the strange little miracle inside: a wish written as a spec, turned into code, compiled into gates, packed and wired by software, checked beat by beat, and finally printed onto a sliver of silicon smaller than your fingernail. That's the IC design flow — and now you've walked the whole road.