The von Neumann bottleneck
Almost any decoder — a linear filter, a Kalman filter, a neural network — is at heart a matrix-vector multiply: weights times features. In conventional digital hardware the weights live in memory and the arithmetic happens in a separate unit, so most of the energy is spent moving weights back and forth across a bus rather than computing with them. This is the von Neumann bottleneck, and for the memory-bound workloads of BCI it dominates the power bill.
Compute-in-memory removes the commute. Instead of fetching weights to an arithmetic unit, it performs the multiply-accumulate inside the memory array, where the weights already are. The dominant energy term — data movement — largely disappears.
A crossbar multiplies with Ohm and Kirchhoff
The canonical device is a memristor / RRAM synapse arranged in a crossbar. Program each device's conductance G_{ij} to store a weight. Apply an input vector as voltages V_i on the rows. By Ohm's law each device passes a current G_{ij}V_i; by Kirchhoff's current law the currents on a column sum automatically. The whole matrix-vector product falls out in a single analog step, in effectively constant time regardless of matrix size.
The crossbar identity: the current summed onto column j is exactly the dot product of the input voltages with the stored conductances. Physics performs the multiply-accumulate — no clocked multiplier, no weight fetch.
The same principle works with subthreshold analog CMOS, where transistors biased in weak inversion act as compact, ultra-low-current silicon synapses and neurons. Whether the substrate is memristive or CMOS, the pitch is identical: let the device physics do the arithmetic.
Energy per operation, near the physical floor
Because the multiply is just charge flowing through a conductance for a short read pulse, the energy per synaptic operation can drop into the femtojoule-to-picojoule range — orders below a digital multiply-and-fetch. For calibration: a biological synapse costs on the order of a few femtojoules per event, and the whole human brain runs on roughly twenty watts. Neuromorphic hardware aims toward that regime, though published figures are usually idealised peaks, not sustained in-system numbers.
Energy of one analog multiply-accumulate: conductance G times read-voltage-squared times read-pulse width au_{\mathrm{rd}}. Lowering V and au_{\mathrm{rd}} cuts energy quadratically and linearly — but also shrinks the signal, so noise and precision push back.
Non-idealities: the catch that keeps it on the bench
Analog computing trades digital's exactness for efficiency, and the bill comes due as non-idealities: device-to-device variability, conductance drift over time, limited bit precision per cell, wire resistance (IR drop) across a large array, stuck or failed devices, temperature dependence and read noise. Each nudges the computed dot product away from the intended one, and those errors accumulate through a deep decoder.
A pragmatic middle path is physical reservoir computing: let a fixed, random, richly dynamical substrate do the hard nonlinear mixing, and train only a simple linear readout on top. Because the reservoir is never trained, device mismatch becomes just part of its fixed identity rather than an error to correct — a graceful way to make imperfect analog hardware useful.