Three walls at once
The classical brain-computer interface pipeline is a division of labour across the skin: electrodes record, a front-end digitises, a radio streams the data out, and a workstation or phone does the decoding. That architecture served Volumes I and II well. But push it along the channel-count scaling curve — from hundreds of channels toward tens of thousands or more — and it collides with three physical walls at the same time.
The first is a bandwidth wall: broadband intracortical data grows linearly with channel count, and wireless telemetry through tissue simply cannot carry it. The second is a power and thermal wall: every milliwatt dissipated by the electronics heats the surrounding brain, which tolerates only a fraction of a degree of chronic warming. The third is a latency wall: any round-trip to external compute adds delay to the feedback loop, and delay degrades closed-loop control.
Raw broadband data rate scales as the product of channel count N, per-channel sampling rate f_s (tens of kHz for spikes) and bit depth b; at high N it reaches gigabits per second.
Concretely, a single high-density probe can produce on the order of hundreds of Mb/s, and a high-density CMOS array scaled toward whole-cortex coverage pushes into the Gb/s regime — far beyond what a safe, low-power radio can move through the skull. You cannot simply stream your way out of this problem.
The neuromorphic answer
Neuromorphic engineering — Carver Mead's original idea — is to build silicon that borrows the brain's own tricks rather than fighting them. Three principles matter here. Represent information as sparse, asynchronous events (spikes) instead of densely sampled waveforms. Co-locate memory and computation so that decoding does not spend most of its energy shuttling weights across a bus. And use event-driven operation so that a circuit spends energy only when something happens.
Applied to a BCI, these principles yield an on-implant neuromorphic co-processor: brain-inspired silicon that reduces the data flood at its source and can decode — or pre-decode — using orders of magnitude less energy than a general-purpose CPU or GPU. It computes where the signal is born, before the bandwidth and latency walls are ever hit.
The rest of this track follows the three pillars in turn: event-driven sensing (guide 2), in-memory analog computation (guide 3), and spiking network decoders with on-chip learning (guide 4). Guide 5 then does the honest accounting — the real power, latency and thermal budgets, and what is actually demonstrated versus merely hoped for.
A co-processor, not a replacement
It is tempting to imagine the whole decoder collapsing onto a single implanted chip. That is not the near-term reality, and pretending otherwise is a common way to overclaim. The realistic role is a front-end co-processor: on-implant spike detection, feature extraction and compression that turn a gigabit torrent into a trickle, which a downstream decoder — possibly still conventional, possibly on an edge device — then interprets.
The design contract for on-implant compute: average power is per-inference energy E_{ ext{inf}} times inference rate f_{ ext{inf}} plus static leakage, and it must fit under a thermal-limited budget. Neuromorphic design attacks both E_{ ext{inf}} and P_{ ext{static}}.