Volatile means forgetful: why DRAM needs the wall socket
Everything we met so far in this rung shares one hidden flaw. DRAM stores a bit as charge in a leaky capacitor, and SRAM stores it in a feedback loop of transistors — but both are volatile: cut the power and the charge drains, the feedback collapses, and the value is simply gone. That is why your computer must reload everything from disk when you turn it on, and why an unsaved document dies in a power cut. Volatile memory is like writing in steam on a mirror; it is wonderfully fast to write and read, but it holds only while you keep breathing on it.
Non-volatile memory is the opposite: it keeps its bits with the power off, for years, like ink on paper. The catch is that the trick used to make a cell remember without power has always cost something — speed, or write endurance, or both. For decades this forced a hard split: a tiny amount of volatile, fast working memory (DRAM) sitting beside a large pool of non-volatile, slow storage (a disk). This is exactly the bottom two floors of the memory hierarchy you climbed in the caches rung, and the whole story of this guide is about what fills — or might finally collapse — the cavern of latency between them.
Flash: the non-volatile memory you already own
The non-volatile memory you almost certainly already own is flash, the heart of every SSD, USB stick, and phone. A flash cell is a transistor with an extra trick: a tiny floating gate, an island of conductor walled off by insulator. Push some electrons onto that island and they stay trapped even with the power off — that trapped charge is the stored bit, and the insulating wall is why flash is non-volatile. To read, the chip simply senses whether the trapped charge shifts the transistor's switching voltage. It is the same floating-gate cell whether it sits in a thumb drive or a data-centre SSD.
Flash has two awkward personalities that shape everything built on it. First, it is read fast but written slowly and erased even more slowly, and you cannot rewrite one byte in place — you must erase a whole large block before you can write fresh data into it. Second, each erase very slightly damages the insulating wall, so a cell wears out after a limited number of write/erase cycles. Modern drives pack 3 or 4 bits into one cell by reading several distinct charge levels, which is wonderfully dense but slower and frailer still. These quirks are exactly why an SSD cannot be plain DRAM-with-persistence; it needs a clever manager.
That manager is the flash translation layer (FTL), a small controller inside the SSD that hides flash's quirks from the operating system. When the OS overwrites a logical block, the FTL does not erase-in-place; it writes the new data to a fresh, already-erased spot and quietly remaps the address, exactly like the address translation you saw in virtual memory but for storage. By spreading writes evenly across all cells — wear levelling — it stops any one block from dying early. So the disk looks like a simple array of rewritable blocks; underneath, the FTL is constantly shuffling, remapping, and erasing in the background to keep that illusion alive.
The dream slot: storage-class and emerging memory
Flash is non-volatile but far too slow and clumsy to be main memory — you address it in big blocks, not single bytes, and writes crawl. So a tantalising gap remains in the hierarchy: a storage-class memory that is byte-addressable and nearly DRAM-fast like RAM, yet persistent and dense like a disk. Fill that slot and the ancient split between fleeting memory and lasting storage starts to dissolve. A whole family of emerging memory technologies is chasing exactly this dream, each storing a bit in some physical state that survives a power cut without the slowness of a floating gate.
Three are worth a name. Phase-change memory (PCM) stores a bit by melting a tiny speck of glassy material into either a crystalline (low-resistance) or amorphous (high-resistance) state — like freezing water into clear ice or cloudy ice and reading which one you see. MRAM stores a bit in the magnetic orientation of a nanoscale layer, switched by spin-polarised current; it is fast and endures essentially unlimited writes, but is harder to make dense. ReRAM (resistive RAM) forms or breaks a microscopic conductive filament to flip resistance. All three are non-volatile and byte-addressable, sitting somewhere in the wide canyon between DRAM and flash.
When a bit flips by itself: ECC and reliability
Memory is not perfectly reliable. A passing cosmic-ray neutron or a stray alpha particle can deposit just enough charge to flip a single DRAM bit from 0 to 1 — a soft error: the data is wrong, but the chip itself is undamaged and will store correctly again next time. On one laptop this is rare enough to ignore, but a data centre with millions of gigabytes sees such flips constantly, and a silently corrupted bit in the wrong place can crash a program or, worse, quietly produce a wrong answer nobody notices.
The defence is ECC, error-correcting code memory. The idea is the same redundancy you would use to guard a phone number: store a few extra check bits alongside each chunk of data so that the hardware, on every read, can recompute them and notice a mismatch. A common scheme called SECDED — single-error-correct, double-error-detect — adds 8 check bits to every 64 data bits, enough to pinpoint and fix any single flipped bit on the fly and to detect (though not fix) any two. The cost is honest and modest: about 12% more memory chips, and a sliver of latency.
data word (no ECC): [ 64 data bits ] -> a flipped bit goes UNNOTICED
with SECDED ECC: [ 64 data bits | 8 check bits ]
on every read, hardware recomputes the 8 check bits:
match -> data is clean, pass it on
1-bit mismatch -> locate the bad bit, FLIP IT BACK, pass clean data
2-bit mismatch -> cannot fix, but REPORT the error (no silent corruption)
cost: 72 bits stored per 64 useful bits ~= +12.5% memoryNotice the shape of this idea, because it recurs everywhere in the upcoming reliability rung. You trade a little extra hardware for dependability — the system keeps working correctly in the presence of faults instead of failing or, far worse, lying. ECC turns an undetected silent error into either a transparently corrected one or a loudly reported one. It does not prevent the cosmic ray; it makes the machine honest about what it cannot store perfectly. The same redundancy-for-trust bargain underlies RAID across disks and the check digits in a credit-card number.
The honest verdict: memory sets the ceiling
Step back across all five guides and one theme dominates. We met SRAM and DRAM, the row buffer and refresh, DDR and channels and bandwidth, HBM and 3D-stacking, and now non-volatile and emerging cells. Through all of it the memory wall stood firm: processor speed has raced ahead while memory latency barely improved, so a DRAM access still costs the CPU hundreds of idle cycles. Caches, prefetching, banking, stacking, and clever controllers fight this gap heroically — but they fight it, they do not erase it. For a huge fraction of real programs, the honest truth is that the memory system, not the cores, sets the performance ceiling.
This reframes the iron law one last time. Run time = instruction count x CPI x cycle time, and on memory-bound code the CPI term is dominated not by arithmetic but by waiting — cycles spent stalled on the memory wall. That is why a faster clock so often disappoints (the megahertz myth again): you cannot clock your way out of a wait that is set by physics on the other side of the chip. The most radical fix on the horizon is to stop moving the data at all — processing in memory, where simple computation happens right inside or beside the memory arrays, attacking the von Neumann bottleneck at its root instead of shuttling bytes back and forth through one narrow doorway.
- Volatile (DRAM, SRAM) forgets at power-off; non-volatile (flash, PCM, MRAM) remembers for years — the trade has always been speed or endurance for that persistence.
- Flash is non-volatile but coarse and slow to write, so an SSD's flash translation layer remaps writes and wear-levels to make it look like a clean rewritable disk.
- Emerging storage-class memories chase the dream slot — DRAM-fast yet persistent — but must beat two fiercely optimised incumbents on cost and density, which is why the dream keeps slipping.
- ECC trades ~12% extra chips to correct single bit flips and flag double ones; and across all five guides, memory latency — not the cores — usually sets the real ceiling.