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Inside a DRAM Chip: Rows, Columns, Refresh

Last guide we learned why DRAM is cheap, dense, and slow — one transistor and one leaky capacitor per bit. Now we open the chip itself: a grid of rows and columns, a clever row buffer that reads a whole row at once, the RAS/CAS dance that picks out a bit, and the refresh that keeps the leaky bits alive. By the end you will see exactly where DRAM's strange timing comes from.

One bit: a transistor and a leaky bucket

From the previous guide we already know the deal: a DRAM bit is just one transistor guarding one tiny capacitor. Charge in the capacitor means 1, empty means 0. That is why DRAM is so wonderfully dense and cheap — barely anything per bit — and also why it is slow and awkward, because a capacitor is a leaky bucket. The charge drains away in milliseconds, and reading it is destructive: to find out whether the bucket held water, you have to tip it out.

Two facts fall straight out of this, and the rest of the chip is built to cope with them. First, because the charge is tiny and reading destroys it, the chip cannot just glance at one bit — it must amplify and rewrite. Second, because the bucket leaks, every bit has to be topped up periodically or it forgets its value. The whole design we are about to meet — rows, a row buffer, the sense amplifiers, the refresh schedule — exists to turn a wall of leaky buckets into something a processor can reliably read and write.

A chip is a grid: rows and columns

The bits are not in a line; they are laid out as a giant two-dimensional grid. To name a bit you give a row and a column, exactly like a seat in a theatre (row J, seat 14). A modern chip packs that grid into several independent banks — think of a bank as a separate sub-grid with its own machinery, so the chip can be working on more than one at a time. Within a bank, picking a row activates an entire row at once; picking a column then selects which slice of that row you actually want.

Why a grid and not a flat line? Cost. A flat array of N bits would need wiring that grows with N; a square grid of roughly sqrt(N) rows by sqrt(N) columns needs far fewer address wires, because the same row-select and column-select circuitry is shared across the whole grid. For a bank of 2^30 bits, a flat scheme is hopeless, but a 2^15-by-2^15 grid needs only 15 row-address bits and 15 column-address bits. The grid is what makes a billion bits per chip affordable.

The row buffer and the RAS/CAS dance

Here is the heart of it. To read a bit, the chip first sends a row-address strobe (RAS): it activates one whole row, dumping every bit in that row down onto the sense amplifiers, which detect the faint charges and latch them into a fast SRAM-like store called the row buffer. Only then does a column-address strobe (CAS) pick out the bytes you wanted from that buffer. The buffer now holds the entire row, hot and ready. These two timings — how long RAS takes to open a row, how long CAS takes to read from the buffer — are the famous RAS/CAS latency numbers on a memory module's spec sheet.

  1. ACTIVATE (RAS): the controller sends a row address; the chosen row's bits flow onto the sense amplifiers and are latched into the row buffer. This is the slow, expensive step.
  2. READ (CAS): the controller sends a column address; the requested bytes are read straight out of the row buffer — fast, because no capacitors are touched, just the latched copy.
  3. More CAS to the same row: while that row stays open, further reads or writes hit the buffer directly — a row-buffer hit, the cheapest access DRAM offers.
  4. PRECHARGE: before a different row in the same bank can open, the current row must be written back (remember, reading was destructive) and the bit-lines reset. Only then can a new ACTIVATE begin.

This explains DRAM's split personality. If your next access lands in the row that is already open, it skips ACTIVATE and PRECHARGE entirely — a row-buffer hit, blazing fast. If it lands in a different row of the same bank, you pay PRECHARGE plus a fresh ACTIVATE plus CAS — a row-buffer miss, several times slower. So DRAM rewards spatial locality at the chip level too: accesses that stay within one open row are cheap, accesses that jump around hammer the slow open/close cycle. The row buffer is, in effect, a one-row cache built into every bank.

Refresh: topping up the leaky buckets

Now the leak. Every capacitor drains, so left alone, a DRAM bit forgets its value in a few tens of milliseconds. The cure is refresh: periodically the chip re-reads each row into the sense amplifiers and writes it straight back, fully recharged. Because an ordinary read already amplifies and rewrites a whole row, refresh is just that mechanism run on a schedule. A controller must walk through every row of every bank within a refresh window — commonly about 64 milliseconds — over and over, forever, just to stop the memory from quietly rotting. This is the refresh that gives Dynamic RAM its 'D'.

Refresh is not free, and the honesty matters. While a row is being refreshed, that bank cannot serve a real request, so refresh steals a slice of bandwidth and adds occasional latency hiccups — a small but real tax, a few percent, that grows as chips get denser and have more rows to walk. By contrast, SRAM needs no refresh at all: it holds its bit in a latching circuit that stays put as long as the power is on. That is one more reason SRAM is faster and simpler per bit, and DRAM cheaper but fussier — the very trade-off from the previous guide, now visible in the timing.

The memory controller conducts the orchestra

Nobody hands raw RAS/CAS/PRECHARGE/refresh commands to the chip by hand. That job belongs to the memory controller, today a block sitting right on the processor die. It takes the simple addresses the cache misses hand it, splits each one into bank, row, and column, and schedules the low-level commands while obeying dozens of timing rules — minimum gaps between ACTIVATE and READ, between PRECHARGE and the next ACTIVATE, and the relentless refresh deadlines. Crucially, it tries to reorder requests so that ones hitting an already-open row go first, turning expensive row-buffer misses into cheap hits where it can.

Banks are the controller's other lever. Because each bank has its own row buffer and machinery, the controller can open a row in bank 1 while bank 0 is still busy precharging — overlapping their slow steps instead of serializing them. This bank-level parallelism is how DRAM delivers high bandwidth despite each individual access being slow: many slow operations run in parallel, so bytes pour out steadily even though any single byte took a long, lonely walk to arrive. It is the same trick a pipeline plays on instructions, applied to memory banks.

Step back and the big honest point appears. All this machinery raises throughput, but it does almost nothing for the latency of a single cold access — opening a fresh row still takes its tens of nanoseconds, the same physics as a decade ago. That is why DRAM bandwidth has climbed far faster than DRAM latency has fallen, and why, by the memory wall, memory so often sets the real performance ceiling. The next guide picks this up directly: how DDR generations, channels, and width multiply bandwidth, and why latency stubbornly refuses to follow.