From one flip-flop to a register that holds a word
In the previous guide we built memory out of nothing but gates: a latch that can hold a single bit, and then the edge-triggered flip-flop that only changes at the instant the clock ticks. One flip-flop remembers one bit — useful, but a computer juggles whole numbers. The fix is wonderfully blunt: line up 32 flip-flops side by side, wire the same clock to all of them, and you have a 32-bit register that captures and holds an entire word at once. There is no clever new idea here, just repetition — width is free once you have the one-bit cell working.
A bare register would overwrite itself every single tick, which is rarely what you want. So real registers get a tiny gate of control: a write-enable signal. When enable is on, the register samples its data input on the next clock edge; when enable is off, it ignores the input and quietly keeps whatever it already held. With that one extra wire, the register becomes a one-word notebook the rest of the machine can write to on command and read from any time — the program counter, the status flags, and the working values mid-computation all live in registers exactly like this.
Group many such registers together, add a way to pick which one to read or write by number, and you have a register file — the CPU's small set of ultra-fast scratchpad slots, the x0..x31 of a RISC-V machine. We will lean on it heavily in later rungs; for now just hold the picture that a register file is just a tidy array of these clocked registers with address lines bolted on.
Synchronous design: one drumbeat for the whole chip
Now picture millions of these registers spread across a chip, with clouds of combinational logic — adders, multiplexers, decoders from earlier in this rung — wired between them. How do you stop chaos, where one block reads a value while a neighbour is still halfway through changing it? The answer is synchronous design, and it is one of the most important disciplines in all of hardware. Every register on the chip listens to the same clock. Nothing moves between registers except on a clock edge. Between edges, the combinational logic is allowed to churn and wobble as much as it likes; nobody is looking yet.
The rhythm is the same every cycle: at the tick, registers all snapshot their inputs simultaneously and lock in new values. Those fresh values then ripple out through the combinational logic between registers — the adder computes a sum, a multiplexer picks a path — and the results race toward the next bank of registers. As long as every result arrives and settles before the following tick, the next snapshot captures correct values, and the machine steps forward cleanly. The whole computer becomes a giant game of statues: everyone scrambles between ticks, freezes on the tick.
Setup and hold: the two promises every signal must keep
There is a catch hiding in "settle before the next tick." A flip-flop is a physical thing; it cannot reliably capture a value that is still wobbling at the exact moment of the clock edge. So each flip-flop comes with two timing promises you must keep. The setup time is how long the input must already be stable before the clock edge. The hold time is how long it must stay stable after the edge. Miss either, and the flip-flop can land in a fuzzy in-between state — neither 0 nor 1 for a while — a genuinely dangerous condition called metastability that can corrupt whatever reads it.
Setup is about the slow path; hold is about the fast path. Think of the clock edge as a camera shutter. Setup time says the subject must hold still for a moment before the shutter clicks, so the picture isn't blurred — the input must arrive early enough. Hold time says the subject must not bolt the instant the shutter opens, or the frame smears — the input must not change too soon after the edge. A good design satisfies both at every flip-flop, on every cycle, with margin to spare against temperature, voltage, and manufacturing wobble.
The critical path: the one slow road that sets the speed limit
Here is the key question synchronous design forces on us: how short can a clock cycle be? It must be long enough that every signal launched from a register at one tick reaches the next register and meets its setup time before the following tick. Some paths through the logic are short and finish with time to spare. But there is always one chain of gates that is the slowest — and that single worst-case path, called the critical path, decides everything. The cycle cannot be shorter than the time light takes down that one road, no matter how fast every other path is.
Think of a marching band that must all arrive at the next line at once. The band can only move as fast as its slowest member: even if everyone else sprints, you wait for the straggler before the whole row may step. Add up the worst chain — the clock-to-output delay of the launching flip-flop, plus every gate delay through the deepest logic cloud, plus the setup time of the catching flip-flop — and that sum is the minimum cycle time. Its reciprocal is the maximum clock rate. So when a spec sheet brags about gigahertz, what it is really reporting is one over the length of the worst path on the chip.
[REG]--->( gate )--->( gate )--->( gate )--->[REG]
A B C D E
clk-to-Q + gate B + gate C + gate D + setup
(launch) (logic delay) (capture)
-----------------------------------------------------
= critical-path delay = T_min
max clock rate = 1 / T_minThis is why architects obsess over the critical path. To run faster, you find that slowest chain and shorten it — replace a slow ripple-carry adder with a faster carry-lookahead design, or break a long logic cloud in two by inserting an extra register in the middle. That last trick, slicing one long path into shorter pipelined stages, is the seed of the whole idea of pipelining you will meet in the next rung. Notice the honest catch, though: cutting the critical path lets you tick faster, but it does nothing on its own to reduce how many cycles a program needs — speed is always instruction count, cycles per instruction, and cycle time together, never the clock alone.
Why this is the hinge of the whole machine
Step back and see what you now hold. Combinational logic computes but forgets; a register remembers. Wire combinational clouds between clocked registers and govern the whole thing with one shared clock, and you have the basic shape of every sequential machine — including the processor itself, which is really just registers (the program counter, the register file, pipeline state) separated by logic (the ALU, decoders, multiplexers), all marching to one beat. The fetch-decode-execute cycle from the foundations rung is this same pattern viewed from far away.
And the critical path is the bridge between this neat digital picture and the brutal physics of real chips. It is why clock rates stopped climbing in the mid-2000s: pushing the cycle ever shorter meant burning ever more power and heat to drive signals down that worst path faster, until the wall became unaffordable. The field's answer was not a faster clock but more work per tick and more cores — exactly the parallelism and accelerators waiting up the ladder. So the humble question "how short can a cycle be?" turns out to be one of the deepest forces shaping modern computer architecture.