Digital Logic & Building Blocks

a truth table

A truth table is the most honest description of a logic function: a chart that lists, for every possible combination of inputs, exactly what the output should be. There is no cleverness to misread — you simply enumerate all cases. If a function has n inputs, the table has 2^n rows, because each input can independently be 0 or 1. It is the spec sheet from which both the human and the algebra start: write what you want row by row, and you have fully defined the circuit.

Reading one is easy. List the inputs as columns on the left, count up in binary down the rows (00, 01, 10, 11 for two inputs), and put the desired output in the right column. For 2-input AND the output column is 0,0,0,1 (only the last row, where both inputs are 1). For OR it is 0,1,1,1. For XOR it is 0,1,1,0 (1 exactly when the inputs differ). To turn a table into gates, look at the rows where the output is 1: each such row gives an AND term of the inputs (using the input directly if it is 1, inverted if it is 0), and you OR those terms together. That recipe, called sum-of-products, always works.

Why it matters: the truth table is ground truth. Any Boolean expression, any Karnaugh-map simplification, any pile of gates is correct if and only if it reproduces the truth table. It is also where size bites: 2^n rows grows explosively, so a function of 16 inputs has 65,536 rows — too many to enumerate by hand, which is why we lean on algebra, K-maps, and computer tools to design and verify large logic instead.

Full truth table for XOR, two inputs A and B. Rows (A,B,out): (0,0,0), (0,1,1), (1,0,1), (1,1,0). Output is 1 only on the two middle rows where A and B disagree — so XOR answers the question 'are these two bits different?', which is exactly what an adder needs to compute a sum bit.

Four rows, one column of answers: the entire behaviour of a 2-input gate, with nothing hidden.

A truth table tells you what a circuit does, never how fast. Two circuits with identical truth tables can differ enormously in gate count and delay — equivalence in logic does not mean equivalence in cost.

Also called
真理表邏輯真值表