Virtual Memory & Memory Mapping

the translation lookaside buffer (TLB)

/ TEE-EL-BEE /

Walking a multi-level page table on every memory access would mean several extra memory reads for every single load and store — crippling. The TLB is a small, very fast cache that remembers recent virtual-page-to-frame translations, so that repeated accesses to the same pages skip the table walk entirely. It is the manager keeping the last few apartment-to-floor lookups on a sticky note instead of opening the big directory each time.

Mechanically, the TLB sits inside the MMU and holds a handful of recent translations (often a few hundred to a couple of thousand). On each access the MMU first checks the TLB by virtual page number: a TLB hit returns the frame immediately, in effectively no extra time; a TLB miss forces the slow page-table walk, after which the new translation is stored in the TLB for next time. Because programs tend to touch the same pages over and over (locality of reference), hit rates are normally very high, which is the only reason paging is fast enough to use everywhere.

The TLB has a sharp consequence worth knowing: it must be kept consistent with the page tables. When the OS changes a mapping (frees a page, switches processes, copies a copy-on-write page), stale TLB entries would translate to the wrong frame, so the OS must flush or invalidate them — and on many designs a full context switch flushes much of the TLB, which is part of why switching processes is costly. TLB misses are also why scattered, cache-unfriendly access patterns run slower than sequential ones, beyond just CPU caches.

A loop that scans an array sequentially touches each page many times in a row: the first access to a page is a TLB miss (slow walk), but the next thousand accesses to that same page are TLB hits. Jumping randomly across a huge array instead causes a TLB miss on almost every access.

Locality turns most accesses into cheap TLB hits.

The TLB caches translations, not data — it is separate from the CPU data caches. Stale entries are a correctness hazard, so the OS must invalidate the TLB when mappings change; a context switch often flushes it, adding to switch cost.

Also called
TLBaddress-translation cache轉譯快取