superscalar execution
Pipelining lets a CPU finish about one instruction per cycle by overlapping stages. A superscalar CPU goes further: it has duplicate hardware so it can fetch, decode, and complete MORE than one instruction in the very same cycle. If a pipeline is one assembly line, a superscalar processor is several assembly lines running side by side, sharing a front end that feeds them.
Concretely, a superscalar core is described by its width — how many instructions it can issue per cycle. A 4-wide core can, in the best case, retire four instructions every clock; modern high-performance cores are often 4- to 8-wide. To do this the chip has multiple copies of execution resources (several arithmetic units, more than one load/store unit, and so on), and per cycle it tries to find several independent instructions it can launch together. The theoretical peak is width instructions per cycle, expressed as IPC (instructions per cycle); real code rarely reaches the peak because it cannot always supply enough independent work.
The deep point for a programmer is that this width is the hardware's ability to exploit instruction-level parallelism, and it is wasted unless your code actually contains independent instructions to run in parallel. A long chain of operations where each depends on the previous one (a dependency chain) cannot fill a wide machine no matter how wide it is — it is limited by latency, not width. This is why two pieces of code with the same instruction count can differ severalfold in speed: one exposes parallelism the superscalar core can soak up, the other is a serial chain that leaves most of the execution units idle every cycle.
s1 += a[i]; s2 += a[i+1]; s3 += a[i+2]; s4 += a[i+3]; with four independent accumulators feeds a 4-wide core four parallel adds per cycle. The naive single-accumulator loop s += a[i] is one dependency chain and runs at the latency of one add, leaving the other units idle.
Same additions, same total — but breaking the dependency chain lets a wide core do them in parallel.
Width is a ceiling, not a guarantee: a perfectly serial dependency chain runs at the same speed on a 2-wide and an 8-wide core. Compilers and programmers must expose independent work for superscalar width to matter.