shufflenet
ShuffleNet (Zhang et al., Megvii, 2018) is an architecture engineered for extremely tight compute budgets, the kind found in low-power mobile and embedded chips, where even MobileNet's cost is too high. Its starting point is that the 1x1 pointwise convolutions, which in MobileNet do the channel mixing, actually dominate the computation in those efficient blocks. A natural way to make 1x1 convolutions cheaper is to make them grouped, splitting channels into groups and convolving each group separately, which cuts cost proportionally to the number of groups. But grouped 1x1 convolutions have a serious side effect: if every layer only mixes channels within its own group, information becomes trapped in separate channel-groups and never crosses between them, which cripples representational power.
ShuffleNet's signature contribution is the channel shuffle operation, a parameter-free, almost-free permutation that fixes exactly this problem. After a grouped convolution, the channels are reorganised so that the next grouped convolution's groups each receive channels drawn from all of the previous groups, restoring information flow across the whole channel space. Picture dealing a deck into several piles, then interleaving them so the next deal mixes cards from every pile; channel shuffle does the same with feature channels. This lets ShuffleNet enjoy the cheapness of grouped 1x1 convolutions without sacrificing cross-group communication.
ShuffleNetV2 (2018) refined the design with an important methodological lesson: FLOPs (the count of multiply-adds) is an imperfect proxy for real speed, because memory access cost and degree of parallelism also matter a great deal on actual hardware. The V2 paper derived practical guidelines, keep input and output channel counts equal to minimise memory traffic, avoid excessive group counts, reduce network fragmentation, and minimise elementwise operations, and redesigned the block around a channel-split plus channel-shuffle structure to be fast in measured latency, not just in theoretical FLOPs. ShuffleNet thus contributed both a concrete efficient primitive (channel shuffle) and the broader insight that efficient design must target real-world latency.
The key takeaway beyond the architecture itself is the FLOPs trap: two models with identical multiply-add counts can have very different real latency, because memory-bound operations and poor parallelism dominate on real chips. ShuffleNetV2's guidelines are a frequently cited corrective to optimising FLOPs alone.