Digital Logic & Building Blocks

a ripple-carry adder

A ripple-carry adder is the most straightforward way to add two multi-bit numbers: line up one full adder per bit position and let the carry flow from each to the next, exactly the way you add on paper, working from the rightmost column leftward. The name captures the picture — a carry generated low down can 'ripple' all the way up the chain, each stage waiting for its neighbour to hand over the carry before it can finish. It is the simplest adder to understand and build, and it is the textbook first step from a single full adder to real arithmetic.

To add two 4-bit numbers, you wire four full adders. The carry-in of the lowest adder is set to 0 (or to 1 to perform subtraction in two's complement). Adder 0 computes sum bit 0 and a carry; that carry becomes adder 1's carry-in; adder 1's carry feeds adder 2; and so on up to adder 3, whose carry-out is the overflow indicator. The catch is timing: adder 3 cannot produce a correct sum until the carry has propagated through adders 0, 1, and 2 first. So the worst-case delay grows linearly with the number of bits — roughly n times the delay of one carry stage for an n-bit adder, which is O(n).

Why it matters and its limit: the ripple-carry adder is the honest baseline — correct, tiny, and easy — but that linear carry delay is exactly the bottleneck on a processor's arithmetic. For a 64-bit add, waiting for a carry to crawl through 64 stages would make the adder the slowest path in the whole chip and cap the clock speed. That is why real processors use faster (but larger) schemes such as carry-lookahead, carry-select, or parallel-prefix adders, which compute the carries ahead of time instead of waiting for them to ripple.

Add 0111 + 0001 with a 4-bit ripple-carry adder. Bit 0: 1+1 = 0, carry 1. Bit 1: 1+0+carry 1 = 0, carry 1. Bit 2: 1+0+carry 1 = 0, carry 1. Bit 3: 0+0+carry 1 = 1, carry 0. Result 1000 (which is 8). Notice the carry rippled through all four stages before the answer was final — that serial wait is the design's weakness.

Carries flow one stage at a time, right to left; the answer is only valid once the last carry settles.

A faster adder gives the identical answer — it does not compute anything different, only sooner. Carry-lookahead and friends trade more gates and area for shorter delay; the ripple-carry adder is correct, just on the critical path.

Also called
RCA漣波加法器行波進位加法器