a pipeline hazard
An assembly line works beautifully only when each load is independent and each machine is free when you need it. Trouble starts when the folding station needs a shirt that the dryer has not finished, or when two loads both want the only dryer at the same minute, or when you do not yet know whether to wash a load at all because someone has not decided. A pipeline hazard is any such situation where an instruction cannot proceed in its scheduled cycle because of a conflict with another instruction in the pipe.
Hazards come in exactly three flavours, and the rest of this field is essentially a tour of them and their cures. A structural hazard is two instructions wanting the same hardware resource in the same cycle — like both needing the single memory port. A data hazard is an instruction needing a value that an earlier, still-in-flight instruction has not yet produced — the answer is computed but not yet written back. A control hazard (branch hazard) is not yet knowing which instruction comes next, because a branch's outcome is still being decided while we would already be fetching the following instruction.
Hazards are why the ideal k-times speedup is never reached. The blunt cure for any hazard is to stall — freeze the front of the pipe and insert do-nothing bubbles until the conflict clears — but stalling wastes cycles. Most of the cleverness in pipeline design is about avoiding stalls: forwarding a result early to dodge most data hazards, duplicating resources to remove structural ones, and predicting branches to hide control ones. Understanding hazards is the heart of understanding why real processors fall short of their paper peak.
Three hazards in three lines. lw x1, 0(x2) then add x3, x1, x4 — a data hazard, because add needs x1 before lw has written it. A branch beq x1, x2, L then the next fetch — a control hazard, because we do not yet know if we jump. Two instructions both reaching memory in one cycle — a structural hazard.
The three hazard families — structural, data, and control — each break the smooth overlap for a different reason.
A hazard is a correctness problem, not just a speed one: if the pipeline ignored it and let an instruction read a stale value, the program would compute the wrong answer. Cures must preserve correct results, then minimise lost cycles.