PCI Express
/ P-C-I express /
PCI Express, almost always shortened to PCIe (say 'pea-see-eye express'), is the standard high-speed interconnect that connects a modern computer's processor to its add-in devices — graphics cards, network cards, and NVMe SSDs. Picture a set of toll-free express lanes leading from the CPU complex out to each peripheral, where you can rent one lane for a slow device or sixteen lanes side by side for a hungry one like a GPU. PCIe is the practical, everyday example to anchor the abstract ideas of buses and interconnects.
Despite the legacy name 'PCI bus', PCIe is not a shared bus at all — it is a switched, point-to-point interconnect. Each connection is a link made of one or more lanes, where each lane is a pair of wires going out and a pair coming back (so traffic flows both directions at once, called full-duplex). Links come in widths written x1, x4, x8, x16 — the number of lanes — and bandwidth scales with both the lane count and the generation: each newer generation roughly doubles the per-lane speed. A switch fans one link out to several devices, and a small protocol wraps the data in packets with addresses and error checks.
PCIe matters because it is where the storage hierarchy meets the rest of the machine: an NVMe SSD plugs straight into PCIe lanes, bypassing the slow legacy disk interfaces, which is a big part of why flash storage became so fast. Two honest cautions. First, the advertised number is peak bandwidth; protocol overhead (the packet headers and encoding) means usable throughput is somewhat lower. Second, a x16 slot does not make a slow device fast — bandwidth only helps a device that can actually fill it, and most devices use far fewer lanes than a GPU.
A GPU sits in a x16 slot to get all sixteen lanes; a Wi-Fi card is happy with a single x1 lane. An NVMe SSD typically uses x4. If a generation gives, say, about 2 GB/s per lane, a x16 link offers roughly sixteen times that — but only the GPU can actually use that much.
Lane count is rented per device's appetite; total bandwidth = per-lane speed x lanes, and only matters if the device can fill it.
The name lies: there is no 'PCI bus' inside PCIe. It kept the old brand for compatibility but is a switched point-to-point interconnect, the opposite of a shared bus.