the page-table base register
/ abbr. PTBR /
Imagine a clerk who must consult a different chart for each customer. The clerk does not memorise every chart; instead a sticky note on the desk says 'today's customer's chart is in drawer 4'. To switch customers, just change the sticky note to point at a different drawer. The PAGE-TABLE BASE REGISTER is that sticky note: a single small hardware register holding the memory address where the CURRENT process's page table begins.
Here is why it exists. Page tables are too big to keep inside the CPU's registers, so each process's page table lives in main memory. The CPU therefore needs to know WHERE in memory the active process's table starts — that starting address is exactly what the page-table base register (PTBR) holds. To translate a logical address, the hardware computes 'PTBR plus page-number times entry-size' to find the right entry in memory, reads the frame number, and proceeds. On a CONTEXT SWITCH, the OS does not copy the whole table anywhere; it simply reloads the PTBR with the new process's table address. That one tiny register change instantly swaps the entire memory map. On x86 this register is called CR3; many systems pair it with a page-table length register that records how many entries are valid.
The PTBR matters because it makes switching address spaces cheap (one register write) and it explains a key performance fact: since the table is in memory, a translation that actually walks the table costs a memory access to read the entry plus another to fetch the data — two accesses where you wanted one. That doubling is the whole motivation for the TLB. A common misconception is that the PTBR holds the page table itself; it does not — it holds only the ADDRESS of the table, which still resides out in main memory.
Process A's page table starts at physical address 0x40000 and process B's at 0x90000. When the scheduler switches from A to B, it just writes 0x90000 into the PTBR (CR3 on x86). No table is copied; every later translation now reads B's table at 0x90000.
Switching address spaces is one register write — reload the PTBR, and the whole memory map changes.
The PTBR holds only the ADDRESS of the page table, not the table itself, which stays in main memory. Because of that, a table walk costs two memory accesses per reference — the exact problem the TLB solves.