Neural front-end ASIC

A neural front-end ASIC is an application-specific integrated circuit that gathers the per-channel signal chain — low-noise amplifier, band-pass filtering, multiplexing, analog-to-digital conversion and digital control — onto one CMOS die placed as close to the electrodes as possible. Putting the front-end at the electrode minimises wire length (hence pickup and parasitics) and is the only way channel counts of hundreds to thousands become physically manageable.

Its design lives in a four-way tension between channel count, per-channel power, input-referred noise and silicon area, further constrained by dynamic range, common-mode and power-supply rejection, and the electrode DC offset it must tolerate. The community benchmarks it with figures like input-referred noise in µV rms, power per channel in µW, area per channel, and the noise-efficiency factor; a good design pushes all of these down at once, which is fundamentally hard because lower noise costs current and current costs heat.

Representative parts span open research and commercial and clinical systems — Intan RHD-family chips, the Neuralink N1 with about 1024 channels, NeuroGrid and various HermesE/C generations — but the recurring lesson is the same: at high channel counts the ASIC's total power, not its transistor count, becomes the ceiling because that power must be dissipated in tissue.