a nested page table
A nested page table is the hardware solution to the same two-level address problem that shadow page tables solved in software. The problem, again: a virtual machine has two layers of address translation — the guest turns guest-virtual into guest-physical, and the hypervisor must turn guest-physical into real-machine-physical. Shadow paging merged these in software at the cost of constant traps. Nested paging instead teaches the CPU to walk both layers by itself, so no merging-by-trapping is needed.
Mechanically, the CPU now holds two sets of page tables at once: the guest's own (guest-virtual to guest-physical) and a second set provided by the hypervisor (guest-physical to machine-physical). On a memory access the hardware page-table walker traverses the guest tables to get a guest-physical address, then feeds that through the hypervisor's tables to reach the real machine address — all in hardware, with the results cached in the TLB just like ordinary translation. Intel markets this as Extended Page Tables (EPT) and AMD as Nested Page Tables (NPT or RVI); generically it is called second-level address translation (SLAT).
The big win is that the guest can edit its own page tables freely without trapping into the hypervisor at all, which removes the heaviest cost of shadow paging and makes memory-heavy workloads much faster. The honest caveat is that a full two-level walk on a TLB miss touches more memory than a single-level walk, so a miss is more expensive — which makes the TLB and large pages matter even more under virtualization. Even so, for almost all modern workloads nested page tables are a clear win over shadow paging.
A guest program reads a variable. On a TLB miss, the CPU hardware walks the guest's page tables to find guest-physical address 0x4000, then walks the hypervisor's tables to discover that guest-physical 0x4000 really lives at machine-physical 0x91000 — and caches the combined result so the next access is instant.
The CPU walks both translation layers in hardware, so the guest never traps to fix mappings.
Nested paging removes the per-edit trap of shadow paging, but a TLB miss now costs a longer two-dimensional page walk, so TLB hits and large pages matter even more inside VMs. It is faster on average, not free.