the cache-coherence protocol (MESI)
/ MESI -> MESS-ee /
Every core has its own L1 (and often L2) cache, so the same memory address can be copied into several caches at once. Now imagine four people each holding a photocopy of the same spreadsheet: the moment one of them edits a cell, every other copy is silently wrong. The cache-coherence protocol is the bookkeeping that prevents this — it guarantees that no core ever reads a stale copy of a line after another core has changed it. MESI is the classic protocol that does this, and its name is the four states a cached line can be in.
Each line in each cache carries one of four MESI states. Modified (M): this core has the only copy and it has been changed (dirty); memory is stale and this core must write it back before anyone else may read it. Exclusive (E): this core has the only copy and it matches memory (clean); it can be written silently, transitioning to M, with no message to other cores. Shared (S): this core has a clean copy and other cores may have clean copies too; reading is free, but writing requires first invalidating the others. Invalid (I): this entry is empty or out of date and must be refetched. The cores talk over an interconnect: when a core wants to write a line that other cores hold in S, it broadcasts an invalidate and waits for them to drop their copies to I — only then may it move the line to M and write. Reading a line another core holds in M forces that core to write back and downgrade. Variants tune this: MESIF adds a Forward state (one sharer is designated to answer requests), and MOESI adds an Owned state (a dirty line can be shared without first writing it back to memory).
This protocol is the hidden machinery behind two costs every concurrent programmer eventually meets. False sharing is expensive precisely because two cores writing one shared line keep bouncing it between their M states, each invalidating the other — even though they touch different bytes. And an atomic read-modify-write must, by definition, acquire the line in an exclusive-like state so no other core can interleave, which is why atomics that are uncontended are cheap but heavily-contended atomics serialize on the coherence traffic. Coherence is automatic and correct, but it is not free.
Two threads on two cores increment counters that live in the same 64-byte line. Core 0 writes -> its line goes M, core 1's copy goes I. Core 1 writes -> it must refetch, core 0's goes I. The line ping-pongs across the interconnect every iteration: a hundredfold slowdown from coherence traffic alone.
The mechanism of false sharing seen through MESI: a clean-looking loop serialized by invalidate-and-refetch.
Coherence keeps caches consistent automatically — it is NOT the same as the language memory model's ordering guarantees. Coherence concerns a single location's copies; visibility and ordering across different locations still require atomics and fences.