the ISA memory model

The ISA memory model is the picture of memory that the architecture promises software. To a program, memory looks like one enormous row of numbered mailboxes, each holding a small chunk of data, and the model spells out the rules of that mailbox row: how the boxes are numbered, how big each one is, how multi-box values are laid out, and which accesses are legal. The actual physical memory (caches, DRAM chips, all of it) is hidden; what software sees is this clean, idealized array.

Three rules make it concrete. First, byte addressing: memory is addressed one byte (8 bits) at a time, so each address picks out a distinct byte, and a 32-bit address space can name 2^32 bytes. Second, alignment: a multi-byte value such as a 4-byte word is normally expected to start at an address that is a multiple of its size (a word at an address divisible by 4); a misaligned access can be slow or, on some machines, illegal. Third, endianness: when a multi-byte number is stored across several byte addresses, the model fixes the order — little-endian puts the least-significant byte at the lowest address, big-endian the most-significant byte first — and software must agree with the hardware on which it is.

This model matters because it is exactly the part of the contract a programmer or compiler must respect to get correct results and to exchange data between machines. Endianness, for instance, is invisible until you save bytes on one machine and read them on another with the opposite order — then the number comes out scrambled. An important clarification: this software-visible model is not the same as the multiprocessor 'memory consistency model', which governs the trickier question of what order one core's writes become visible to another core; that is a separate, deeper topic.