Instruction-Level Parallelism & Out-of-Order Execution

in-order commit and precise exceptions

Think again of the kitchen that cooks in any order but serves plates strictly in the order taken. The moment a plate is actually placed in front of a diner is the moment that order becomes 'official'. In a CPU, that moment is called commit (or retirement): the point at which an instruction's effects are written into the visible architectural state — the real registers and memory — for good. In-order commit means this making-official happens in the original program order, even though the cooking (execution) happened in any order.

Why insist on order at commit when execution is a free-for-all? Because of exceptions and interrupts. A precise exception means that when an instruction faults — a divide by zero, a page fault, an illegal instruction — the machine can stop in a clean state where every instruction before the faulting one has fully completed and every instruction after it has had no visible effect at all. That clean boundary is exactly what an operating system needs to handle the fault (e.g. bring in the missing page) and then resume as if nothing strange happened. In-order commit, driven by the reorder buffer, manufactures this clean boundary: at the head of the ROB you simply check 'did this instruction fault?' before letting it change anything, and if so you discard it and everything younger.

The honest framing: out-of-order cores execute speculatively and out of order for speed, but commit converts all that chaos back into the simple sequential story the programmer and OS expect. Precise exceptions are not a luxury — without them, debugging, virtual memory (restartable page faults), and reliable interrupt handling would be nearly impossible. The cost is that an instruction cannot truly finish until all older instructions have committed, which is why a single long-latency instruction at the ROB head can stall retirement and eventually back up the whole window.

A load at the ROB head triggers a page fault. The OS must resume exactly here: every earlier instruction has committed, none later has. After the OS loads the page, execution restarts at that load with the register and memory state perfectly precise.

Commit in program order so that a fault always lands on a clean, restartable boundary.

Imprecise exceptions (where some later instructions already altered state) were a real headache on early machines. Precise exceptions are what make virtual memory and ordinary debugging feasible, which is why every general-purpose CPU provides them.

Also called
retirementin-order retirementprecise interrupts退役精確中斷