the complexity and power cost of ILP

Extracting instruction-level parallelism is not free hardware magic; it is paid for in transistors, design complexity, and especially electrical power. Picture hiring a large back-office team whose only job is to figure out which tasks can be done in parallel — they get the real work done faster, but they themselves consume salary, space, and coffee. In a CPU, the renaming tables, reservation stations, reorder buffer, branch predictors, and wakeup/select logic are that overhead: a lot of energetic machinery devoted not to computing your answer but to discovering and managing parallelism around it.

Concretely, the cost grows worse than linearly with how aggressive the core is. Doubling the out-of-order window means more entries to search and compare every cycle; the wakeup-and-select logic that decides which waiting instructions can fire scales roughly with the square of issue width and window size, and it switches at full clock speed, burning dynamic power (which goes as capacitance times voltage^2 times frequency). Worse, much of this energy is spent speculatively — on wrong-path instructions that get squashed — so it does real electrical work for zero useful result. A meaningful fraction of a high-performance core's power goes to this 'overhead of being clever' rather than to arithmetic.

This is the crux of why ILP hit a wall as a strategy. Once Dennard scaling ended and the power wall arrived in the mid-2000s, the energy cost of squeezing out a few more percent of single-thread performance became prohibitive — you spend disproportionately more watts for diminishing speed. Several simpler cores deliver more total work per watt than one enormous out-of-order core, which is exactly the economic argument behind multicore and, further on, domain-specific accelerators. The honest summary: out-of-order ILP is brilliant engineering, but it is power-hungry and its returns diminish, which reshaped the whole industry.