Deserializer

The deserializer is the receive half of a SerDes: it catches the fast incoming bit stream and fans it back out into a wide, slow parallel word the rest of the chip can digest. Think of a high-speed conveyor belt dropping one item per tick into a row of 32 bins; after 32 ticks you lift out a full tray of 32 parallel bits at 1/32 the speed. To do this it must first decide where each bit begins — which is exactly what clock-and-data recovery provides — and then demultiplex with a tree of 1:2 stages mirroring the serializer.

Before the demux can run, the deserializer's front end has to make the smeared, attenuated signal legible again: a CTLE and DFE clean up the channel's distortion, a sampler decides 1-vs-0, and the recovered clock places the sampling instant in the middle of each bit's 'eye'. Only then does word alignment (using a known training pattern or comma symbol) tell the parallel output where the byte boundaries actually are, so the bits land in the right bins.