Dataflow architecture
A normal processor follows a program counter — a single finger pointing at 'do this instruction, now the next'. A dataflow architecture throws that away and lets the data itself decide the order: an operation fires the instant all of its inputs have arrived, no matter where it sits, just like a recipe where you can chop the onions, boil the water, and warm the pan in any order — each step starts the moment its ingredients are ready rather than waiting for a line number.
Physically, a dataflow accelerator lays out the computation in space rather than time: it maps a whole graph of operations onto a grid of processing elements, and results stream directly from one PE to the next instead of bouncing through registers and memory in between. This eliminates the constant instruction-fetch and memory traffic of a classic CPU, exposing huge natural parallelism — which is why dataflow ideas underpin many modern AI accelerators (systolic arrays are a structured special case). The catch is that mapping arbitrary, irregular programs onto a fixed spatial fabric is hard, so dataflow shines for regular, repetitive workloads.
Classic 1980s general-purpose dataflow machines failed to displace the von Neumann CPU, but the idea returned triumphantly inside today's domain-specific AI chips, where the workload is regular enough to map cleanly.