the Harvard architecture
Recall the von Neumann workshop with one shelf and one hallway for both instruction sheets and parts. The Harvard architecture is the same workshop with two separate shelves and two separate hallways — one set just for instructions, one set just for data. Now the boss can grab the next instruction sheet at the very same moment a part is being carried to the workbench, because they never share a corridor.
Technically, a Harvard machine has separate memories and separate paths (buses) for instructions and data, so an instruction fetch and a data access can happen at once instead of taking turns. This sidesteps the von Neumann bottleneck for those two operations and raises memory bandwidth. The cost is rigidity and complexity: code and data live in different places, which makes it harder to treat a program as ordinary data the way the stored-program idea encourages.
Pure Harvard machines are common in small embedded chips and digital signal processors, where the predictable speed is worth the rigidity. But here is the honest twist for everyday computers: they are mostly von Neumann at the architecture level (one address space, programs are data) yet split instructions and data into separate first-level caches inside the chip. This split-cache trick is often called a modified Harvard architecture — von Neumann's flexibility on the outside, Harvard's parallelism on the inside.
Most modern CPUs use split L1 caches: an L1 instruction cache and a separate L1 data cache. The core can fetch an instruction and read a data value in the same cycle — Harvard-style parallelism layered on a von Neumann main memory.
Real chips often blend both: von Neumann memory, Harvard caches.
Do not imagine it is Harvard versus von Neumann as a winner-take-all fight. Mainstream computers are von Neumann at the architecture level and modified-Harvard at the cache level — they borrow from both.