false dependences (WAR and WAW)

Imagine two cooks who would gladly work in parallel, except the kitchen only has one bowl labelled 'mixing bowl', so they keep waiting for each other to free it up — not because one needs the other's food, but because they are fighting over the same container. A false dependence is exactly this: two instructions are forced to wait on each other not because real data flows between them, but only because they happen to reuse the same register name. Give each its own bowl and the conflict vanishes.

There are two kinds, alongside the one real kind. The true dependence is read-after-write (RAW): instruction B reads a value instruction A produced, so B genuinely must wait. The false ones are: write-after-read (WAR, an anti-dependence) — B writes a register that an earlier A still needs to read, so B must not overwrite it too soon; and write-after-write (WAW, an output dependence) — A and B both write the same register, and the last write must win. In WAR and WAW no value actually passes from one instruction to the other; the only thing being shared is the name of a register. That is why they are called name dependences, and why they are 'false'.

This matters enormously for parallelism. A processor has only a few dozen architectural register names, so a busy instruction stream constantly reuses them, manufacturing false dependences that would needlessly serialize independent work. The cure is register renaming: give each write a fresh physical register so WAR and WAW dependences simply disappear, leaving only the true RAW dependences that the algorithm genuinely requires. Removing false dependences is one of the biggest reasons out-of-order cores find so much more parallelism than the register count would suggest.