Energy per operation / per-inference budget

The standard efficiency metric for neuromorphic hardware is energy per synaptic operation (often quoted in picojoules or femtojoules per multiply-accumulate or per spike-driven update) and, at task level, energy per inference. These let architectures be compared independent of clock or workload, and they expose why analog in-memory and event-driven designs are pursued: they attack the data-movement energy that dominates digital MAC.

Honest comparison requires whole-system, iso-accuracy numbers: peripheral converters, memory access, routing, and idle/leakage power must be counted, not just the core array, and the operation count must be for a task solved to the same quality. Cherry-picked per-operation figures that omit these overheads are a recurring source of overclaiming in the field.