steady-state error

Steady-state error is the stubborn gap left between where you wanted the system to end up and where it actually settles, after all the transients have died away. Picture a cruise control set to 100 km/h that holds rock-steady at 97 — that lingering 3 km/h is the steady-state error. It's the difference between a loop that's merely stable and one that's actually accurate; a system can settle calmly and still settle at the wrong place.

Whether you get this offset depends on the 'type' of your loop — how many pure integrators (1/s factors) sit in the forward path. A type-0 system (no integrator) always leaves a finite error for a constant command, because it needs a non-zero error just to generate enough output. Add one integrator (type 1) and the constant-command error vanishes to zero — the integrator keeps accumulating until the error is exactly gone — but a ramp command still leaves a constant error. This is precisely why the 'I' term in PID is so prized: it adds an integrator, driving steady-state error for a step input to zero. The trade is that integrators add phase lag, nudging the loop toward instability.