the phase-locked loop (PLL)
/ P-L-L /
A phase-locked loop is a feedback system that makes one oscillator track and lock onto the phase of an incoming reference signal, so its output stays perfectly in step. Picture a backing musician listening to a metronome and continuously adjusting their tempo to stay exactly on the beat: if they drift ahead they slow down, if they fall behind they speed up. A PLL does that electrically, constantly nudging its internal oscillator until it matches the reference's frequency and phase.
It has three core parts working in a loop. A phase detector compares the phase of the reference against the phase of the loop's own oscillator and outputs an error signal proportional to how far apart they are. A loop filter (a low-pass) smooths that error into a steady control voltage. That voltage drives a voltage-controlled oscillator (a VCO), whose output is fed back to the phase detector. The loop settles, or locks, when the VCO runs at exactly the reference frequency with a fixed phase relationship, so the error is constant. Crucially, if you put a frequency divider in the feedback path that divides by N, the VCO must run N times faster than the reference to keep the loop locked, so the PLL becomes a frequency multiplier: feed in a clean low-frequency reference and get a clean high-frequency output that is a chosen multiple of it.
That multiplier trick is why PLLs are everywhere: they synthesize the many precise radio frequencies in a phone or radio from one crystal, generate the fast internal clocks of a CPU from a slow board crystal, recover the clock hidden in a stream of serial data, and demodulate FM. The honest orientation-level notes: a PLL is itself a feedback loop, so it must be designed for stability (the loop filter sets how fast it locks and whether it overshoots or rings), it takes time to acquire lock and only works within a limited capture range, and its output carries phase noise and jitter inherited partly from the reference and partly from the VCO.
A radio uses a PLL with a divide-by-100 in the feedback and a 1 MHz crystal reference. To stay locked, the VCO must run at 100 times 1 MHz equals 100 MHz. Change the divider to 101 and the output jumps to 101 MHz: one crystal, a whole band of precise channels.
A PLL locks a VCO to a reference; a divide-by-N in the loop makes it a frequency multiplier.
A PLL is a feedback loop, so loop-filter design trades lock speed against stability and jitter; too aggressive and it rings or oscillates. It only locks within a limited capture range and takes finite time to acquire, so it is not an instantaneous frequency source.